Data Sheet

MLX90640 32x24 IR array
Datasheet
Page 18 of 60
REVISION 11 – 3 AUGUST 2018
Figure 13 I
2
C configuration register (0x800F) bits meaning
10.7.2.
10.7.2.10.7.2.
10.7.2. RAM
RAMRAM
RAM
Figure 14 RAM memory map (Chess pattern mode) – factory default mode
Figure 15 RAM memory map (Interleaved mode)
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
Melexis reserved
SDA driver
current limit control I2C threshold levels
FM+ disable
I2C configuration register - 0x800F
0 FM+ mode enabled (default)
1 FM+ mode disabled
0 VDD reffered threshold (normal mode) (default)
1 1.8V reffered threshold (1.8V mode)
0 SDA driver current limit is ON (default)
1 SDA driver current limit is OFF
0 Melexis reserved
- - - - - - - - - - - - Melexis reserved
Melexis reserved
0x0400
1 2 … … 31 32
0x041F
0x0420
33 34 … … 63 64
0x043F
0x0440
65 66 … … 95 96
0x045F
0x0460
…
0x06A0
0x047F
…
0x06BF
0x06C0
705 706 … … 735 736
0x06DF
0x06E0
737 738 … … 767 768
0x06FF
0x0700
0x0700=Ta_Vbe, 0x0708=CP(SP 0), 0x070A=GAIN Melexis reserved
0x071F
0x0720
0x0720=Ta_PTAT, 0x0728=CP(SP1), 0x072A=VDDpix Melexis reserved
0x073F
Subpage 0 Subpage 1
…
0x0400 0x041F
0x0420 0x043F
0x0440 0x045F
0x0460
…
0x06A0
0x047F
…
0x06BF
0x06C0 0x06DF
0x06E0 0x06FF
0x0700 0x071F
0x0720 0x073F
0x0720=Ta_PTAT, 0x0728=CP(SP1), 0x072A=VDDpix Melexis reserved
Pixels 33...64 (subpage 1)
Pixels 65…96 (subpage 0)
…
Pixels 705…736 (subpage 0)
Pixels 737…768 (subpage 1)
0x0700=Ta_Vbe, 0x0708=CP(SP 0), 0x070A=GAIN Melexis reserved
Pixels 1…32 (subpage 0)