Data Sheet

SCL
REG
SDA
IN/TRIG
EN
OUT±
V
DD
GND
OUT+
VDD/NC
9
10
8
7
6
2
1
3
4
5
DRV2605L
SLOS854C –MAY 2014–REVISED SEPTEMBER 2014 www.ti.com
DGS Package
10-Pin VSSOP
(Top View)
Pin Functions
PIN
TYPE
(1)
DESCRIPTION
NO. NAME
1 REG O The REG pin is the 1.8-V regulator output. A 1-µF capacitor required
2 SCL I I
2
C clock
3 SDA I/O I
2
C data
Multi-mode Input. I
2
C selectable as PWM, analog, or trigger. If not used, this pin should
4 IN/TRIG I
be connected to GND
5 EN I Device enable
6 V
DD
/NC P Optional supply input. This pin should be tied to V
DD
or left floating.
7 OUT+ O Positive haptic driver differential output
8 GND P Supply ground
9 OUT– O Negative haptic driver differential output
10 V
DD
P Supply Input (2to 5.2 V). A 1-µF capacitor is required.
(1) I = input, O = output, I/O = input and output, P = power
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