Datasheet

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AS621x
Register Description
Datasheet • PUBLIC
DS000677 • v2-00 • 2020-Feb-24
36 │ 30
Figure 33:
Timing Diagram for Word Read
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
1
0
0
R
/
W
0
0
0
0
0
0
IX
1
IX
0
Start
by master
Values are defined by
ADD
0
pin setting
Frame
1
:
Slave Address Byte
Frame
2
:
Index Register Byte
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
Frame
3
:
Slave Address
Byte
Frame
4
:
Register MSB
Data Byte
D
6
D
5
D
4
D
3
D
2
D
1
D
7
D
0
(
Continued
)
(
Continued
)
Acknowledge
by slave
Acknowledge
by slave
Acknowledge
by slave
Stop
by master
1
0
0
R
/
W
Start
by master
Acknowledge
by master
1
2
3
4
5
6
7
8
9
Frame
5
:
Register LSB
Data Byte
D
6
D
5
D
4
D
3
D
2
D
1
D
7
D
0
Acknowledge
by master
Stop
by master
A3
A2
A1
A0
A3
A2
A1
A0
Values are defined
by ALERT/ADD1 pin
setting