Datasheet
Table Of Contents
- Content Guide
- 1 General Description
- 2 Ordering Information
- 3 Pin Assignment
- 4 Absolute Maximum Ratings
- 5 Operating Conditions
- 6 Register Description
- 6.1 Register Overview
- 6.2 Detailed Register Description
- 6.3 Serial Interface
- 6.3.1 Bus Description
- 6.3.2 Data Interface
- 6.3.3 Bus Address
- 6.3.4 Read/Write Operation
- 6.3.5 Slave Operation
- 6.3.6 Slave Receiver Mode
- 6.3.7 Slave Transmitter
- 6.3.8 Alert Function
- 6.3.9 High Speed Mode
- 6.3.10 General Call
- 6.3.11 Start Byte
- 6.3.12 Timeout Function
- 6.3.13 Bus Conditions
- 6.3.14 Timing Characteristics
- 6.3.15 Timing Diagrams
- 7 Application Information
- 8 Package Drawings & Markings
- 9 Revision Information
- 10 Legal Information
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AS621x
Register Description
Datasheet • PUBLIC
DS000677 • v2-00 • 2020-Feb-24
36 │ 29
6.3.15 Timing Diagrams
The following timing diagrams depict the different bus operation modes and data transmission:
Figure 32:
Timing Diagram for Word Write
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
1
0
0
R
/
W
0
0
0
0
0
0
IX
1
IX
0
Start
by master
Values are defined by
ADD
0
pin setting
Frame
1
:
Slave Address Byte
Frame
2
:
Index Register Byte
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
Frame
3
:
MSB Data Byte
Frame
4
:
LSB Data Byte
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
6
D
5
D
4
D
3
D
2
D
1
D
7
D
0
(
Continued
)
(
Continued
)
Acknowledge
by slave
Acknowledge
by slave
Acknowledge
by slave
Acknowledge
by slave
Stop
by master
A3
A2
A1
A0
Values are defined
by ALERT/ADD1 pin
setting