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AS621x
Register Description
Datasheet • PUBLIC
DS000677 • v2-00 • 2020-Feb-24
36 │ 28
6.3.14 Timing Characteristics
Figure 30:
Serial Interface Timing Diagram
Figure 31:
Bus Timing Specifications
Parameter
Symbol
Fast Mode
High Speed Mode
Unit
Min
Max
Min
Max
SCL clock frequency
f
SCL
0.001
0.4
0.001
3.4
MHz
Bus free time between STOP
and START condition
t
BUF
600
160
ns
Hold time after repeated
START condition
t
HDSTA
100
100
ns
Repeated START condition
setup time
t
SUSTA
100
100
ns
Data in hold time
t
HDDAT
0
0
ns
Data out hold time
(1)
t
DH
100
100
ns
Data setup time
t
SUDAT
100
10
ns
SCL clock low period
t
LOW
1300
160
ns
SCL clock high period
t
HIGH
600
60
ns
Clock/Data fall time
t
F
300
80
ns
Clock/Data rise time
t
R
300
80
ns
Clock/Data rise time for
SCL≤100 kHz
t
R
1000
ns
(1) The device will hold the SDA line high for 100 ns during the falling edge of the SCL.