Datasheet
Table Of Contents
- Content Guide
- 1 General Description
- 2 Ordering Information
- 3 Pin Assignment
- 4 Absolute Maximum Ratings
- 5 Operating Conditions
- 6 Register Description
- 6.1 Register Overview
- 6.2 Detailed Register Description
- 6.3 Serial Interface
- 6.3.1 Bus Description
- 6.3.2 Data Interface
- 6.3.3 Bus Address
- 6.3.4 Read/Write Operation
- 6.3.5 Slave Operation
- 6.3.6 Slave Receiver Mode
- 6.3.7 Slave Transmitter
- 6.3.8 Alert Function
- 6.3.9 High Speed Mode
- 6.3.10 General Call
- 6.3.11 Start Byte
- 6.3.12 Timeout Function
- 6.3.13 Bus Conditions
- 6.3.14 Timing Characteristics
- 6.3.15 Timing Diagrams
- 7 Application Information
- 8 Package Drawings & Markings
- 9 Revision Information
- 10 Legal Information
Document Feedback
AS621x
Register Description
Datasheet • PUBLIC
DS000677 • v2-00 • 2020-Feb-24
36 │ 27
6.3.13 Bus Conditions
The following conditions occur on the serial bus which is compatible to the I²C-Bus.
Bus Idle
The signals SDA and SCL are not actively driven and pulled to a high level by an external pull-up
resistor.
Start Data Transfer
A transition of the SDA input from high to low level while the SCL signal is kept at high level results in
a START condition. Such a START condition must precede any data transfer.
Stop Data Transfer
A transition of the SDA input from low to high level while the SCL signal is kept at high level results in
a STOP condition. Any data transfer is finished by generating a STOP or START condition.
Data Transfer
The master device defines the number of data bytes between a START and STOP condition and there
is no limitation in the amount of data to be transmitted.
If it is desired to read only a single MSB byte without the LSB byte, a termination of the data transfer
can be provoked by issuing a START or STOP condition on the bus.
Acknowledge
It is mandatory for each slave device to respond with acknowledge if the device is addressed by the
master. Acknowledge is indicated by pulling down the data line (SDA) while the clock signal (SCL) is
high in the acknowledge clock phase. In order to avoid an unwanted START or STOP condition on the
bus, setup and hold times must be met.
The master can signal an end of data transmission by transmitting a Not-Acknowledge on the last
transmitted data byte by keeping the acknowledge bit at high level.