Datasheet
Table Of Contents
- Content Guide
- 1 General Description
- 2 Ordering Information
- 3 Pin Assignment
- 4 Absolute Maximum Ratings
- 5 Operating Conditions
- 6 Register Description
- 6.1 Register Overview
- 6.2 Detailed Register Description
- 6.3 Serial Interface
- 6.3.1 Bus Description
- 6.3.2 Data Interface
- 6.3.3 Bus Address
- 6.3.4 Read/Write Operation
- 6.3.5 Slave Operation
- 6.3.6 Slave Receiver Mode
- 6.3.7 Slave Transmitter
- 6.3.8 Alert Function
- 6.3.9 High Speed Mode
- 6.3.10 General Call
- 6.3.11 Start Byte
- 6.3.12 Timeout Function
- 6.3.13 Bus Conditions
- 6.3.14 Timing Characteristics
- 6.3.15 Timing Diagrams
- 7 Application Information
- 8 Package Drawings & Markings
- 9 Revision Information
- 10 Legal Information
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AS621x
Register Description
Datasheet • PUBLIC
DS000677 • v2-00 • 2020-Feb-24
36 │ 25
Similarly to the byte transfer where the MSB is transmitted first, the transfer of a 16-bit word is
executed by a two byte transfer whereas the MSB byte is always transmitted first.
6.3.5 Slave Operation
The device employs a slave functionality only (slave transmitter and slave receiver) and cannot be
operated as a bus master. Consequently, the device never actively drives the SCL line.
6.3.6 Slave Receiver Mode
Any transmission is invoked by the master device by transmitting the slave address with a low R/W bit.
Subsequently, the slave device acknowledges the reception of the valid address by pulling the ninth
bit to a low level. Following to acknowledge, the master transmits the content of the index register.
This transfer is again acknowledged by the slave device. The next data byte(s) are written to the
actual data register which is selected by the index register while each transfer is acknowledged upon a
completed transfer by the slave device. A data transfer can be finished if the master transmits a
START or a STOP condition on the bus.
6.3.7 Slave Transmitter
The master transmits the slave address with a high R/W bit. In turn, the slave acknowledges a valid
slave address. Subsequently, the slave transmits the MSB byte of the actual selected data register by
the index register. After the MSB byte transmission, acknowledge is sent by the master. Afterwards,
the LSB byte is transmitted by the slave which is also acknowledged by the master after the
completed transmission. The data transfer can be terminated by the master by transmitting a Not-
Acknowledge after the transmitted slave data or by invoking a START or a STOP condition on the bus.
6.3.8 Alert Function
If the device is configured for an interrupt mode operation (IM=1), the ALERT output can be used as
an alert signal.
If the polarity bit is set to ‘0’ (POL=’0’), the alert condition bit is set to ‘0’ in case the temperature has
exceeded the configured value in register THIGH. Accordingly, the alert condition bit is set to ‘1’ if the
temperature has fallen below the configured value in register TLOW.
If the polarity bit is set to ‘1’ (POL=’1’), the alert condition bit is inverted. The following table
summarizes the status of the alert condition bit with different alert conditions and polarity
configurations.