Datasheet

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AS621x
Register Description
Datasheet • PUBLIC
DS000677 • v2-00 • 2020-Feb-24
36 │ 23
In order to address a specific device, a START condition has to be generated by the master device by
pulling the data line (SDA) from a logic high level to a logic low level while the serial clock signal (SCL)
is kept at high level.
After the start condition, the slave address byte is transmitted which is completed with a ninth bit which
indicates a read (bit=’1’) or a write operation (bit=’0’) respectively. All slaves read the data on the rising
edge of the clock. An acknowledge signal is generated by the addressed slave during the ninth clock
pulse. This acknowledge signal is produced by pulling the pin SDA to a low level by the selected
slave.
Subsequently, the byte data transfer is started and finished by an acknowledge bit. A change in the
data signal (SDA) while the clock signal (SCL) is high causes a START or STOP condition. Hence, it
must be ensured such a condition is prevented during a data transfer phase.
After completing the data transfer, the master generates a STOP condition by pulling the data line
(SDA) from low level to high level while the clock signal (SCL) is kept at high level.
6.3.2 Data Interface
A bus connection is created by connecting the open drain input/output lines SDA and SCL to the two
wire bus. The inputs of SDA and SCL feature Schmitt-trigger inputs as well as low pass filters in order
to suppress noise on the bus line. This improves the robustness against spikes on the two wire
interface.
Both fast transmission mode (1kHz to 400kHz) and high-speed transmission mode (1kHz to 3.4MHz)
are employed to cover different bus speed settings.
Any data transfer transmits the MSB first and the LSB as last bit.
6.3.3 Bus Address
A slave address consists of seven bits, followed by a data direction bit (read/write operation). The
slave address can be selected from 8 different address settings by connecting the pin ADD0 and
ADD1 to an appropriate signal as summarized in Figure 28.
The ADD0 and the ADD1 pin must not be left unconnected.
The address selection with ADD1 is depending on the usage of the ALERT function (described in
chapter 6.3.8). In case the ALERT functionality is used, it must be connected via a pull up resistor to
VDD. In case the ALERT functionality is not used, the pin must be connected to either SCL or VSS
(refer to Figure 28 for details).