Datasheet
Table Of Contents
- Content Guide
- 1 General Description
- 2 Ordering Information
- 3 Pin Assignment
- 4 Absolute Maximum Ratings
- 5 Operating Conditions
- 6 Register Description
- 6.1 Register Overview
- 6.2 Detailed Register Description
- 6.3 Serial Interface
- 6.3.1 Bus Description
- 6.3.2 Data Interface
- 6.3.3 Bus Address
- 6.3.4 Read/Write Operation
- 6.3.5 Slave Operation
- 6.3.6 Slave Receiver Mode
- 6.3.7 Slave Transmitter
- 6.3.8 Alert Function
- 6.3.9 High Speed Mode
- 6.3.10 General Call
- 6.3.11 Start Byte
- 6.3.12 Timeout Function
- 6.3.13 Bus Conditions
- 6.3.14 Timing Characteristics
- 6.3.15 Timing Diagrams
- 7 Application Information
- 8 Package Drawings & Markings
- 9 Revision Information
- 10 Legal Information
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AS621x
Register Description
Datasheet • PUBLIC
DS000677 • v2-00 • 2020-Feb-24
36 │ 18
6.2.9 High and Low Limit Registers
If the comparator mode is configured (IM=0), the ALERT output becomes active if the temperature
equals or exceeds the defined value in register THIGH for the configured number of consecutive
faults (N). This configuration is defined by the field CF in the configuration register. The ALERT output
remains assigned until the converted temperature value equals or falls below the defined value in
register TLOW for the same number of consecutive fault cycles.
If the interrupt mode is configured (IM=1), the ALERT output becomes active if the temperature equals
or exceeds the defined value in register THIGH for the configured number of consecutive fault cycles.
It remains active until a read operation is executed on any register. The ALERT output is also cleared
if the device is set into sleep mode by setting bit SM in the configuration register.
Once the ALERT output is cleared, it is activated again only if the temperature value falls below the
configured value in register TLOW. It remains active unless a read operation has taken place.
This sequence is repeated unless the device is set into the comparator mode. This reset command
clears the interrupt mode bit and consequently puts the device into the comparator mode.
The sequential behavior is summarized in the following Figure 23.