Datasheet
Table Of Contents
- Content Guide
- 1 General Description
- 2 Ordering Information
- 3 Pin Assignment
- 4 Absolute Maximum Ratings
- 5 Operating Conditions
- 6 Register Description
- 6.1 Register Overview
- 6.2 Detailed Register Description
- 6.3 Serial Interface
- 6.3.1 Bus Description
- 6.3.2 Data Interface
- 6.3.3 Bus Address
- 6.3.4 Read/Write Operation
- 6.3.5 Slave Operation
- 6.3.6 Slave Receiver Mode
- 6.3.7 Slave Transmitter
- 6.3.8 Alert Function
- 6.3.9 High Speed Mode
- 6.3.10 General Call
- 6.3.11 Start Byte
- 6.3.12 Timeout Function
- 6.3.13 Bus Conditions
- 6.3.14 Timing Characteristics
- 6.3.15 Timing Diagrams
- 7 Application Information
- 8 Package Drawings & Markings
- 9 Revision Information
- 10 Legal Information
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AS621x
Register Description
Datasheet • PUBLIC
DS000677 • v2-00 • 2020-Feb-24
36 │ 13
Addr: 0x1
Bit
Bit Name
Default
Access
Bit Description
14
Reserved
1
RO
Reserved
15
SS
0
RW
Single Shot
The configuration register is a 16-bit register which defines the operation modes of the device. Any
read/write operation processes the MSB byte first.
In Figure 13 the configuration register is shown. The bits 0-4 and 13-14 are not to be used and are set
to read only. The explanation of the other bits are detailed in the following sections.
6.2.2 Alert Bit
The alert bit can be used to easily compare the current temperature reading to the thresholds that can
be set in the TLWO and THIGH registers.
If the polarity bit is set to 0, the AL bit is read as 1 until the converted temperature value exceeds the
defined value in the high temperature threshold register THIGH for the number of defined consecutive
faults (bits CF). Such an event causes the AL bit to toggle to 0 and the value is kept until the
converted temperature value falls below the defined value in the low temperature threshold register
TLOW for the number of defined consecutive faults. If this condition is met, the AL bit is reset to 1.
The polarity bit (POL) defines the active state of the alert bit as depicted in the following figure.
The alert bit has the same setting as the alert output as long as the device is configured for the
comparator mode.
Figure 14:
State Diagram of the Alert Bit