Datasheet

Table Of Contents
9.51 I3C_BUS_AVB (62h)
I3C_BUS_AVB register (r/w)
Table 140. I3C_BUS_AVB register
0
(1)
0
(1)
0
(1)
I3C_Bus_Avb
_Sel1
I3C_Bus_Avb
_Sel0
0
(1)
0
(1)
PD_DIS_
INT1
1. This bit must be set to '0' for the correct operation of the device.
Table 141. I3C_BUS_AVB register description
PD_DIS_INT1
This bit allows disabling the INT1 pull-down.
(0: Pull-down on INT1 enabled (pull-down is effectively connected only when no interrupts are routed
to the INT1 pin or when I3C dynamic address is assigned);
1: Pull-down on INT1 disabled (pull-down not connected)
I3C_Bus_Avb_Sel[1:0]
These bits are used to select the bus available time when I3C IBI is used.
Default value: 00
(00: bus available time equal to 50 µsec (default);
01: bus available time equal to 2 µsec;
10: bus available time equal to 1 msec;
11: bus available time equal to 25 msec)
9.52 INTERNAL_FREQ_FINE (63h)
Internal frequency register (r)
Table 142. INTERNAL_FREQ_FINE register
FREQ_
FINE7
FREQ_
FINE6
FREQ_
FINE5
FREQ_
FINE4
FREQ_
FINE3
FREQ_
FINE2
FREQ_
FINE1
FREQ_
FINE0
Table 143. INTERNAL_FREQ_FINE register description
FREQ_FINE[7:0]
Difference in percentage of the effective ODR (and Timestamp Rate) with respect to the typical. Step:
0.15%. 8-bit format, 2's complement.
LSM6DSO
I3C_BUS_AVB (62h)
DS12140 - Rev 2
page 81/172