Datasheet

Table Of Contents
9.41 TAP_CFG0 (56h)
Activity/inactivity functions, configuration of filtering, and tap recognition functions (r/w)
Table 117. TAP_CFG0 register
0
INT_CLR_
ON_READ
SLEEP_
STATUS_
ON_INT
SLOPE_FDS TAP_X_EN TAP_Y_EN TAP_Z_EN LIR
Table 118. TAP_CFG0 register description
INT_CLR_ON_READ
This bit allows immediately clearing the latched interrupts of an event detection upon the read of
the corresponding status register. It must be set to 1 together with LIR. Default value: 0
(0: latched interrupt signal cleared at the end of the ODR period;
1: latched interrupt signal immediately cleared)
SLEEP_STATUS_ON_INT
Activity/inactivity interrupt mode configuration.
If INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits are enabled, drives the sleep status or
sleep change on the INT pins. Default value: 0
(0: sleep change notification on INT pins; 1: sleep status reported on INT pins)
SLOPE_FDS
HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions. Default value: 0 (
0: SLOPE filter applied; 1: HPF applied)
TAP_X_EN
Enable X direction in tap recognition. Default value: 0
(0: X direction disabled; 1: X direction enabled)
TAP_Y_EN
Enable Y direction in tap recognition. Default value: 0
(0: Y direction disabled; 1: Y direction enabled)
TAP_Z_EN
Enable Z direction in tap recognition. Default value: 0
(0: Z direction disabled; 1: Z direction enabled)
LIR
Latched Interrupt. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
LSM6DSO
TAP_CFG0 (56h)
DS12140 - Rev 2
page 73/172