Datasheet

Table Of Contents
9.8 COUNTER_BDR_REG2 (0Ch)
Counter batch data rate register 2 (r/w)
Table 35. COUNTER_BDR_REG2 register
CNT_BDR_
TH_7
CNT_BDR_
TH_6
CNT_BDR_
TH_5
CNT_BDR_
TH_4
CNT_BDR_
TH_3
CNT_BDR_
TH_2
CNT_BDR_
TH_1
CNT_BDR_
TH_0
Table 36. COUNTER_BDR_REG2 register description
CNT_BDR_TH_[7:0]
In conjunction with CNT_BDR_TH_[10:8] in COUNTER_BDR_REG1 (0Bh), sets the threshold for the
internal counter of batching events. When this counter reaches the threshold, the counter is reset and
the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’.
9.9 INT1_CTRL (0Dh)
INT1 pin control register (r/w)
Each bit in this register enables a signal to be carried out on INT1 when the MIPI I3C
SM
dynamic address is not
assigned (I²C or SPI is used). Some bits can be also used to trigger an IBI (In-Band Interrupt) when the MIPI
I3C
SM
interface is used. The output of the pin will be the OR combination of the signals selected here and in
MD1_CFG (5Eh).
Table 37. INT1_CTRL register
DEN_DRDY
_flag
INT1_
CNT_BDR
INT1_
FIFO_FULL
INT1_
FIFO_OVR
INT1_
FIFO_TH
INT1_
BOOT
INT1_
DRDY_G
INT1_
DRDY_XL
Table 38. INT1_CTRL register description
DEN_DRDY_flag Sends DEN_DRDY (DEN stamped on Sensor Data flag) to INT1 pin
INT1_CNT_BDR Enables COUNTER_BDR_IA interrupt on INT1
INT1_FIFO_FULL
Enables FIFO full flag interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3C
SM
interface is used.
INT1_FIFO_OVR
Enables FIFO overrun interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3C
SM
interface is used.
INT1_FIFO_TH
Enables FIFO threshold interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3C
SM
interface is used.
INT1_BOOT Enables boot status on INT1 pin
INT1_DRDY_G
Enables gyroscope data-ready interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI
I3C
SM
interface is used.
INT1_DRDY_XL
Enables accelerometer data-ready interrupt on INT1 pin. It can be also used to trigger an IBI when the
MIPI I3C
SM
interface is used.
LSM6DSO
COUNTER_BDR_REG2 (0Ch)
DS12140 - Rev 2
page 48/172