Datasheet

6.5.6 Bypass-to-FIFO mode
In Bypass-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = '111'), data measurement storage inside FIFO
operates in FIFO mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode).
FIFO behavior changes according to the trigger event detected in one of the following interrupt events:
• Single tap
• Double tap
• Wake-up
• Free-fall
• D6D
6.5.7 FIFO reading procedure
The data stored in FIFO are accessible from dedicated registers and each FIFO word is composed of 7 bytes:
one tag byte (FIFO_DATA_OUT_TAG (78h), in order to identify the sensor, and 6 bytes of fixed data
(FIFO_DATA_OUT registers from (79h) to (7Eh)).
The DIFF_FIFO_[9:0] field in the FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh) registers contains the number
of words (1 byte TAG + 6 bytes DATA) collected in FIFO.
In addition, it is possible to configure a counter of the batch events of accelerometer or gyroscope sensors. The
flag COUNTER_BDR_IA in FIFO_STATUS2 (3Bh) alerts that the counter reaches a selectable threshold
(CNT_BDR_TH_[10:0] field in COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch)). This allows
triggering the reading of FIFO with the desired latency of one single sensor. The sensor is selectable using the
TRIG_COUNTER_BDR bit in COUNTER_BDR_REG1 (0Bh). As for the other FIFO status events, the flag
COUNTER_BDR_IA can be routed on the INT1 or INT2 pins by asserting the corresponding bits
(INT1_CNT_BDR of INT1_CTRL (0Dh) and INT2_CNT_BDR of INT2_CTRL (0Eh)).
In order to maximize the amount of accelerometer and gyroscope data in FIFO, the user can enable the
compression algorithm by setting to 1 both the FIFO_COMPR_EN bit in EMB_FUNC_EN_B (05h) (embedded
functions registers bank) and the FIFO_COMPR_RT_EN bit in FIFO_CTRL2 (08h). When compression is
enabled, it is also possible to force writing non-compressed data at a selectable rate using the
UNCOPTR_RATE_[1:0] field in FIFO_CTRL2 (08h).
Meta information about accelerometer and gyroscope sensor configuration changes can be managed by enabling
the ODR_CHG_EN bit in FIFO_CTRL2 (08h).
LSM6DSO
FIFO
DS12140 - Rev 2
page 34/172