Datasheet

6.5 FIFO
The presence of a FIFO allows consistent power saving for the system since the host processor does not need
continuously poll data from the sensor, but It can wake up only when needed and burst the significant data out
from the FIFO.
The LSM6DSO embeds 3 kbytes of data in FIFO (up to 9 kbytes with the compression feature enabled) to store
the following data:
• Gyroscope
• Accelerometer
• External sensors (up to 4)
• Step counter
• Timestamp
• Temperature
Writing data in the FIFO can be configured to be triggered by the:
• Accelerometer / gyroscope data-ready signal
• Sensor hub data-ready signal
• Step detection signal
The applications have maximum flexibility in choosing the rate of batching for physical sensors with FIFO-
dedicated configurations: accelerometer, gyroscope and temperature sensor batching rates can be selected by
the user. External sensor writing in FIFO can be triggered by the accelerometer data-ready signal or by an
external sensor interrupt. The step counter can be stored in FIFO with associated timestamp each time a step is
detected. It is possible to select decimation for timestamp batching in FIFO with a factor of 1, 8, or 32.
The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG byte that allows
recognizing the meaning of a word in FIFO.
FIFO allows correct reconstruction of the timestamp information for each sensor stored in FIFO. If a change in the
ODR or BDR (Batching Data Rate) configuration is performed, the application can correctly reconstruct the
timestamp and know exactly when the change was applied without disabling FIFO batching. FIFO stores
information of the new configuration and timestamp in which the change was applied in the device.
Finally, FIFO embeds a compression algorithm that the user can enable in order to have up to 9 kbytes of data
stored in FIFO and take advantage of interface communication length for FIFO flushing and communication power
consumption.
The programmable FIFO watermark threshold can be set in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h) using the
WTM[8:0] bits. To monitor the FIFO status, dedicated registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh))
can be read to detect FIFO overrun events, FIFO full status, FIFO empty status, FIFO watermark status and the
number of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and INT2 pins of
these status events, the configuration can be set in INT1_CTRL (0Dh) and INT2_CTRL (0Eh).
The FIFO buffer can be configured according to six different modes:
• Bypass mode
• FIFO mode
• Continuous mode
• Continuous-to-FIFO mode
• Bypass-to-continuous mode
• Bypass-to-FIFO mode
Each mode is selected by the FIFO_MODE_[2:0] bits in the FIFO_CTRL4 (0Ah) register.
6.5.1 Bypass mode
In Bypass mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 000), the FIFO is not operational and it remains
empty. Bypass mode is also used to reset the FIFO when in FIFO mode.
LSM6DSO
FIFO
DS12140 - Rev 2
page 32/172