Datasheet

5.3 I²C/I3C coexistence in LSM6DSO
In the LSM6DSO, the SDA and SCL lines are common to both I²C and I3C. The I²C bus requires anti-spike filters
on the SDA and SCL pins that are not compatible with I3C timing.
The device can be connected to both I²C and I3C or only to the I3C bus depending on the connection of the INT1
pin when the device is powered up:
• INT1 pin floating (internal pull-down): I²C/I3C both active, see Figure 13
• INT1 pin connected to VDD_IO: only I3C active, see Figure 14
Figure 13. I²C and I3C both active (INT1 pin not connected)
1. Address assignment (DAA or ENTDA) must be performed with I²C Fast Mode Plus Timing. When the slave
is addressed, the I²C slave is disabled and the timing is compatible with I3C specifications.
Figure 14. Only I3C active (INT1 pin connected to VDD_IO)
1. When the slave is I3C only, the I²C slave is always disabled. The address can be assigned using I3C SDR
timing.
LSM6DSO
I²C/I3C coexistence in LSM6DSO
DS12140 - Rev 2
page 25/172