Datasheet

Table Of Contents
5 Digital interfaces
5.1 I²C/SPI interface
The registers embedded inside the LSM6DSO may be accessed through both the I²C and SPI serial interfaces.
The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The device is compatible
with SPI modes 0 and 3.
The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the CS line must be tied
high (i.e connected to Vdd_IO).
Table 8. Serial interface pin description
Pin name Pin description
CS
SPI enable
I²C/SPI mode selection (1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
SCL/SPC
I²C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
SDA/SDI/SDO
I²C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SDO/SA0
SPI Serial Data Output (SDO)
I²C less significant bit of the device address
5.1.1 I²C serial interface
The LSM6DSO I²C is a bus slave. The I²C is employed to write the data to the registers, whose content can also
be read back.
The relevant I²C terminology is provided in the table below.
Table 9. I²C terminology
Term Description
Transmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master The device which initiates a transfer, generates clock signals and terminates a transfer
Slave The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the Serial DAta line (SDA). The
latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be
connected to Vdd_IO through external pull-up resistors. When the bus is free, both the lines are high.
The I²C interface is implemented with fast mode (400 kHz) I²C standards as well as with the standard mode.
In order to disable the I²C block, (I2C_disable) = 1 must be written in CTRL4_C (13h).
LSM6DSO
Digital interfaces
DS12140 - Rev 2
page 17/172