Datasheet

4.4.2 I²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Table 6. I²C slave timing values
Symbol Parameter
I²C standard mode
(1)
I²C fast mode
(1)
Unit
Min Max Min Max
f
(SCL)
SCL clock frequency 0 100 0 400 kHz
t
w(SCLL)
SCL clock low time 4.7 1.3
µs
t
w(SCLH)
SCL clock high time 4.0 0.6
t
su(SDA)
SDA setup time 250 100 ns
t
h(SDA)
SDA data hold time 0 3.45 0 0.9 µs
t
h(ST)
START condition hold time 4 0.6
µs
t
su(SR)
Repeated START condition setup time 4.7 0.6
t
su(SP)
STOP condition setup time 4 0.6
t
w(SP:SR)
Bus free time between STOP and START condition 4.7 1.3
1. Data based on standard I²C protocol requirement, not tested in production.
Figure 6. I²C slave timing diagram
t
su(SP)
t
w(SCLL)
t
su(SDA)
t
su(SR)
t
h(ST)
t
w(SCLH)
t
h(SDA)
t
w(SP:SR)
START
REPEATED
START
START
STOP
SDA
SCL
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO for both ports.
LSM6DSO
Communication interface characteristics
DS12140 - Rev 2
page 14/172