Datasheet

4.4 Communication interface characteristics
4.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 5. SPI slave timing values (in mode 3)
Symbol
Parameter
Value
(1)
Unit
Min Max
t
c(SPC)
SPI clock cycle 100 ns
f
c(SPC)
SPI clock frequency 10 MHz
t
su(CS)
CS setup time 5
ns
t
h(CS)
CS hold time 20
t
su(SI)
SDI input setup time 5
t
h(SI)
SDI input hold time 15
t
v(SO)
SDO valid output time 50
t
h(SO)
SDO output hold time 5
t
dis(SO)
SDO output disable time 50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production
Figure 5. SPI slave timing diagram (in mode 3)
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO for both input and output ports.
LSM6DSO
Communication interface characteristics
DS12140 - Rev 2
page 13/172