Datasheet

11.37 EMB_FUNC_ODR_CFG_B (5Fh)
Finite State Machine output data rate configuration register (r/w)
Table 247. EMB_FUNC_ODR_CFG_B register
0
(1)
1
(2)
0
(1)
FSM_ODR1 FSM_ODR0
0
(1)
1
(2)
1
(2)
1. This bit must be set to '0' for the correct operation of the device.
2. This bit must be set to '1' for the correct operation of the device.
Table 248. EMB_FUNC_ODR_CFG_B register description
FSM_ODR[1:0]
Finite State Machine ODR configuration:
(00: 12.5 Hz;
01: 26 Hz (default);
10: 52 Hz;
11: 104 Hz)
11.38 STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h)
Step counter output register (r)
Table 249. STEP_COUNTER_L register
STEP_7 STEP_6 STEP_5 STEP_4 STEP_3 STEP_2 STEP_1 STEP_0
Table 250. STEP_COUNTER_L register description
STEP_[7:0] Step counter output (LSbyte)
Table 251. STEP_COUNTER_H register
STEP_15 STEP_14 STEP_13 STEP_12 STEP_11 STEP_10 STEP_9 STEP_8
Table 252. STEP_COUNTER_H register description
STEP_[15:8] Step counter output (MSbyte)
LSM6DSO
EMB_FUNC_ODR_CFG_B (5Fh)
DS12140 - Rev 2
page 121/172