Datasheet

Table Of Contents
11.13 FSM_STATUS_A (13h)
Finite State Machine status register (r)
Table 197. FSM_STATUS_A register
IS_FSM8 IS_FSM7 IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1
Table 198. FSM_STATUS_A register description
IS_FSM8
Interrupt status bit for FSM8 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM7
Interrupt status bit for FSM7 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM6
Interrupt status bit for FSM6 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM5
Interrupt status bit for FSM5 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM4
Interrupt status bit for FSM4 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM3
Interrupt status bit for FSM3 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM2
Interrupt status bit for FSM2 interrupt event.
(1: interrupt detected; 0: no interrupt)
IS_FSM1
Interrupt status bit for FSM1 interrupt event.
(1: interrupt detected; 0: no interrupt)
LSM6DSO
FSM_STATUS_A (13h)
DS12140 - Rev 2
page 100/172