Datasheet

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Table Of Contents

LGA-14L

(2.5 x 3.0 x 0.83 mm) typ.

Features

• Power consumption: 0.55 mA in combo high-performance mode

• “Always-on" experience with low power consumption for both accelerometer and

gyroscope

• Smart FIFO up to 9 kbyte

• Android compliant

• ±2/±4/±8/±16 g full scale

• ±125/±250/±500/±1000/±2000 dps full scale

• Analog supply voltage: 1.71 V to 3.6 V

• Independent IO supply (1.62 V)

• Compact footprint: 2.5 mm x 3 mm x 0.83 mm

• SPI / I²C & MIPI I3C

serial interface with main processor data synchronization

• Auxiliary SPI for OIS data output for gyroscope and accelerometer

• Advanced pedometer, step detector and step counter

• Significant Motion Detection, Tilt detection

• Standard interrupts: free-fall, wakeup, 6D/4D orientation, click and double-click

• Programmable Finite State Machine: accelerometer, gyroscope and external

sensors

• Embedded temperature sensor

• ECOPACK

, RoHS and “Green” compliant

Applications

• Motion tracking and gesture detection

• Sensor hub

• Indoor navigation

• IoT and connected devices

• Smart power saving for handheld devices

• EIS and OIS for camera applications

• Vibration monitoring and compensation

Description

The LSM6DSO is a system-in-package featuring a 3D digital accelerometer and a 3D

digital gyroscope boosting performance at 0.55 mA in high-performance mode and

enabling always-on low-power features for an optimal motion experience for the

consumer.

The LSM6DSO supports main OS requirements, offering real, virtual and batch

sensors with 9 kbytes for dynamic data batching. ST’s family of MEMS sensor

modules leverages the robust and mature manufacturing processes already used for

the production of micromachined accelerometers and gyroscopes. The various

sensing elements are manufactured using specialized micromachining processes,

while the IC interfaces are developed using CMOS technology that allows the design

of a dedicated circuit which is trimmed to better match the characteristics of the

sensing element.

Product status link

LSM6DSO

Product summary

Order code LSM6DSO LSM6DSOTR

Temperature

range [°C]

-40 to +85

Package

LGA-14L

(2.5 x 3 x 0.83 mm)

Packing Tray Tape & Reel

Product label

iNEMO inertial module: always-on 3D accelerometer and 3D gyroscope

LSM6DSO

Datasheet

DS12140 - Rev 2 - January 2019

For further information contact your local STMicroelectronics sales office.

www.st.com

Summary of content (172 pages)

PAGE 1
LSM6DSO Datasheet iNEMO inertial module: always-on 3D accelerometer and 3D gyroscope Features LGA-14L (2.5 x 3.0 x 0.83 mm) typ.
PAGE 2
LSM6DSO The LSM6DSO has a full-scale acceleration range of ±2/±4/±8/±16 g and an angular rate range of ±125/±250/±500/±1000/±2000 dps. The LSM6DSO fully supports EIS and OIS applications as the module includes a dedicated configurable signal processing path for OIS and auxiliary SPI, configurable for both the gyroscope and accelerometer. High robustness to mechanical shock makes the LSM6DSO the preferred choice of system designers for the creation and manufacturing of reliable products.
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LSM6DSO Overview 1 Overview The LSM6DSO is a system-in-package featuring a high-performance 3-axis digital accelerometer and 3-axis digital gyroscope. The LSM6DSO delivers best-in-class motion sensing that can detect orientation and gestures in order to empower application developers and consumers with features and capabilities that are more sophisticated than simply orienting their devices to portrait and landscape mode.
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LSM6DSO Embedded low-power features 2 Embedded low-power features The LSM6DSO has been designed to be fully compliant with Android, featuring the following on-chip functions: • 9 kybtes data buffering, data can be compressed two or three times – 100% efficiency with flexible configurations and partitioning – Possibility to store timestamp • • • 2.
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LSM6DSO Finite State Machine Figure 1. Generic state machine Finite State Machine in the LSM6DSO The LSM6DSO works as a combo accelerometer-gyroscope sensor, generating acceleration and angular rate output data. It is also possible to connect an external sensor (magnetometer) by using the Sensor Hub feature (Mode 2). These data can be used as input of up to 16 programs in the embedded Finite State Machine (Figure 2. State machine in the LSM6DSO).
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LSM6DSO Pin description 3 Pin description Figure 3. Pin connections 3.1 Pin connections The LSM6DSO offers flexibility to connect the pins in order to have four different mode connections and functionalities.
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LSM6DSO Pin connections Figure 4.
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LSM6DSO Pin connections Pin# 12 13 Name CS SCL Mode 1 function Mode 2 function Mode 3 / Mode 4 function I²C/MIPI I3CSM/SPI mode selection I²C/MIPI I3CSM/SPI mode selection I²C/MIPI I3CSM/SPI mode selection (1: SPI idle mode / I²C/MIPI I3CSM communication enabled; (1: SPI idle mode / I²C/MIPI I3CSM communication enabled; 0: SPI communication mode / I²C/MIPI I3CSM disabled) 0: SPI communication mode / I²C/ 0: SPI communication mode / I²C/ MIPI I3CSM disabled) SM MIPI I3C disabled) I²C/MIPI I3
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LSM6DSO Module specifications 4 Module specifications 4.1 Mechanical characteristics @ Vdd = 1.8 V, T = 25 °C, unless otherwise noted. Table 2. Mechanical characteristics Symbol Parameter Test conditions Min. Typ.(1) Max. Unit ±2 LA_FS ±4 Linear acceleration measurement range ±8 g ±16 ±125 ±250 G_FS Angular rate measurement range ±500 dps ±1000 ±2000 LA_So G_So G_So% LA_SoDr G_SoDr LA_TyOff G_TyOff FS = ±2 g 0.061 FS = ±4 g 0.122 FS = ±8 g 0.244 FS = ±16 g 0.
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LSM6DSO Mechanical characteristics Symbol RMS Parameter Test conditions Acceleration RMS noise in normal/low-power mode(9) (10) Acceleration RMS noise in ultra-low-power mode(9)(10) Min. Typ.(1) FS = ±2 g 1.8 FS = ±4 g 2.0 FS = ±8 g 2.4 FS = ±16 g 3.0 FS = ±2 g 5.5 Max. Unit mg(RMS) 1.6(11) 12.5 26 52 104 LA_ODR Linear acceleration output data rate 208 416 833 1666 3332 6664 Hz 12.
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LSM6DSO Mechanical characteristics 13. The linear acceleration self-test output change is defined with the device in stationary condition as the absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 0.061 mg at ±2 g full scale. 14. Accelerometer self-test limits are full-scale independent. 15. The sign of the angular rate self-test output change is defined by the STx_G bits in a dedicated register for all axes. 16.
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LSM6DSO Electrical characteristics 4.2 Electrical characteristics @ Vdd = 1.8 V, T = 25 °C, unless otherwise noted. Table 3. Electrical characteristics Min. Typ.(1) Max. Unit Supply voltage 1.71 1.8 3.6 V Power supply for I/O 1.62 3.6 V Symbol Vdd Vdd_IO Parameter Test conditions Gyroscope and accelerometer current consumption in high-performance mode 0.
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LSM6DSO Communication interface characteristics 4.4 Communication interface characteristics 4.4.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 5.
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LSM6DSO Communication interface characteristics 4.4.2 I²C - inter-IC control interface Subject to general operating conditions for Vdd and Top. Table 6. I²C slave timing values Symbol I²C standard mode(1) Parameter f(SCL) I²C fast mode (1) Min Max Min Max 0 100 0 400 SCL clock frequency tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0 th(ST) START condition hold time 4 0.
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LSM6DSO Absolute maximum ratings 4.5 Absolute maximum ratings Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7. Absolute maximum ratings Symbol Maximum value Unit Vdd Supply voltage -0.3 to 4.
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LSM6DSO Terminology 4.6 Terminology 4.6.1 Sensitivity Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor.
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LSM6DSO Digital interfaces 5 Digital interfaces 5.1 I²C/SPI interface The registers embedded inside the LSM6DSO may be accessed through both the I²C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The device is compatible with SPI modes 0 and 3. The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the CS line must be tied high (i.e connected to Vdd_IO). Table 8.
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LSM6DSO I²C/SPI interface I²C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy.
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LSM6DSO I²C/SPI interface Slave SAK SAK SAK DATA DATA DATA Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state.
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LSM6DSO I²C/SPI interface 5.1.2 SPI bus interface The LSM6DSO SPI is a bus slave. The SPI allows writing and reading the registers of the device. The serial interface communicates to the application using 4 wires: CS, SPC, SDI and SDO. Figure 7. Read and write protocol (in mode 3) CS SPC SDI RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CS is the serial port enable and it is controlled by the SPI master.
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LSM6DSO I²C/SPI interface Figure 9. Multiple byte SPI read protocol (2-byte example) (in mode 3) CS SPC SDI RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14DO13DO12 DO11DO10 DO9 DO8 SPI write Figure 10. SPI write protocol (in mode 3) CS SPC SDI RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 AD6 AD5 AD4 AD3 AD2 AD1 AD0 The SPI Write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.
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LSM6DSO I²C/SPI interface Figure 12. SPI read protocol in 3-wire mode (in mode 3) CS SPC SDI/O DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 The SPI read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is also available in 3-wire mode.
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LSM6DSO MIPI I3CSM interface 5.2 MIPI I3CSM interface 5.2.1 MIPI I3CSM slave interface The LSM6DSO interface includes a MIPI I3CSM SDR only slave interface (compliant with release 1.
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LSM6DSO MIPI I3CSM interface Command Command code Default Description 0x00 GETMRL 0x8C 0x10 0x09 Get maximum read length during private read (3 byte) 0x02 0x08 GETPID 0x8D 0x00 0x6C Device ID register 0x10 0x0B GETBCR 0x8E GETDCR 0x8F 0x07 (1 byte) 0x44 default Bus characteristics register MIPI I3CSM Device Characteristic Register 0x00 GETSTATUS 0x90 0x00 Status register (2 byte) 0x00 GETMXDS 0x94 0x20 Return max data speed (2 byte) DS12140 - Rev 2 page 24/172
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LSM6DSO I²C/I3C coexistence in LSM6DSO 5.3 I²C/I3C coexistence in LSM6DSO In the LSM6DSO, the SDA and SCL lines are common to both I²C and I3C. The I²C bus requires anti-spike filters on the SDA and SCL pins that are not compatible with I3C timing.
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LSM6DSO Master I²C interface 5.4 Master I²C interface If the LSM6DSO is configured in Mode 2, a master I²C line is available. The master serial interface is mapped in the following dedicated pins. Table 16. Master I²C pin details Pin name MSCL I²C serial clock master MSDA I²C serial data master MDRDY 5.5 Pin description I²C master external synchronization signal Auxiliary SPI interface If the LSM6DSO is configured in Mode 3 or Mode 4, the auxiliary SPI is available.
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LSM6DSO Functionality 6 Functionality 6.1 Operating modes In the LSM6DSO, the accelerometer and the gyroscope can be turned on/off independently of each other and are allowed to have different ODRs and power modes.
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LSM6DSO Block diagram of filters 6.4 Block diagram of filters Figure 15. Block diagram of filters M E M S S E N S O R Gyro UI/OIS front-end ADC1 Regs array, FIFO Low Pass UI XL XL UI/OIS front-end Low Pass OIS Gyro ADC2 Temperature sensor Voltage and current references 6.4.
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LSM6DSO Block diagram of filters Figure 17. Accelerometer composite filter LOW_PASS_ON_6D Free-fall 0 Advanced functions 1 LPF2_XL_EN USR_OFF_ON_OUT HP_SLOPE_XL_EN 0 0 Digital LP Filter 1 LPF1 output (1) 0 USER OFFSET LPF2 1 USR_OFF_W OFS_USR[7:0] FIFO HPCF_XL[2:0] Digital HP Filter 6D / 4D 1 1 0 0 Wake-up Activity / Inactivity SPI / I 2C / MIPI I3C SM USR_OFF_ON_WU SLOPE_FDS 001 010 … 111 1 HPCF_XL[2:0] SLOPE FILTER 000 HPCF_XL[2:0] S/D Tap 1.
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LSM6DSO Block diagram of filters Note: 6.4.2 Mode 4 is enabled when Mode4_EN = 1 and OIS_EN_SPI2 = 1 in CTRL1_OIS (70h). The configuration of the accelerometer UI chain is not affected by enabling Mode 4. Accelerometer output values are in registers OUTX_L_A (28h) and OUTX_H_A (29h) through not found and ODR at 6.66 kHz. Accelerometer full-scale management between the UI chain and OIS chain depends on the setting of the XL_FS_MODE bit in register CTRL8_XL (17h).
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LSM6DSO Block diagram of filters • Mode 3 / Mode 4 (for OIS and EIS functionality) Figure 20. Gyroscope digital chain - Mode 3 / Mode 4 (OIS/EIS) Digital LP Filter LPF2 (3) HP_EN_G ADC 0 Digital HP Filter FIFO 1 ODR_G[3:0] SPI / I2C / MIPI I3CSM HP_EN_OIS 1 (3) Digital(1) (2) LP Filter LPF1 SPI_Aux 0 ODR Gyro @6.6 kHz FTYPE[1:0]_OIS 1. 2. 3. When Mode3/4 is enabled, the LPF1 filter is not available in the gyroscope UI chain.
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LSM6DSO FIFO 6.5 FIFO The presence of a FIFO allows consistent power saving for the system since the host processor does not need continuously poll data from the sensor, but It can wake up only when needed and burst the significant data out from the FIFO.
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LSM6DSO FIFO 6.5.2 FIFO mode In FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 001) data from the output channels are stored in the FIFO until it is full. To reset FIFO content, Bypass mode should be selected by writing FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0]) to '000'. After this reset command, it is possible to restart FIFO mode by writing FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0]) to '001'.
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LSM6DSO FIFO 6.5.6 Bypass-to-FIFO mode In Bypass-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = '111'), data measurement storage inside FIFO operates in FIFO mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode). FIFO behavior changes according to the trigger event detected in one of the following interrupt events: • Single tap • Double tap • Wake-up • Free-fall • D6D 6.5.
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LSM6DSO Application hints 7 Application hints 7.1 LSM6DSO electrical connections in Mode 1 Figure 21. LSM6DSO electrical connections in Mode 1 CS SCL SDA Mode 1 HOST 14 12 I 2C / SM SDO/SA0 TOP VIEW SDx SCx 4 INT1 8 C2 7 GND VDDIO 5 NC NC GND GND or VDDIO 11 1 MIPI I3C / SPI (3/4-w) (1) (1) LSM6DSO Vdd INT2 VDD C1 100 nF I2C configuration GND Vdd_IO Rpu Vdd_IO 100 nF GND Rpu SCL SDA Pull-up to be added Rpu=10kOhm 1.
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LSM6DSO LSM6DSO electrical connections in Mode 2 7.2 LSM6DSO electrical connections in Mode 2 Figure 22. LSM6DSO electrical connections in Mode 2 HOST CS SCL SDA Mode 2 I 2C / SM 14 SDO/SA0 1 12 11 TOP VIEW MSDA MSCL 8 C2 GND 7 GND VDDIO 5 NC NC 4 INT1 MIPI I3C / SPI (3/4-w) LSM6DSO (1) (1) Master I2C MDRDY/INT2 Vdd LSM6DSM External LSM6DSM sensors VDD C1 100 nF I2C configuration GND Vdd_IO Rpu Vdd_IO 100 nF GND Rpu SCL SDA Pull-up to be added Rpu=10kOhm 1.
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LSM6DSO LSM6DSO electrical connections in Mode 3 and Mode 4 7.3 LSM6DSO electrical connections in Mode 3 and Mode 4 SPC CS SDI Figure 23.
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DS12140 - Rev 2 Table 19.
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DS12140 - Rev 2 pin# Name Mode 1 function Mode 2 function Mode 3 / Mode 4 function Pin status Mode 1 Pin status Mode 2 Pin status Mode 3/4 (1) 13 SCL I²C/MIPI I3CSM serial clock (SCL) / SPI serial port clock (SPC) I²C/MIPI I3CSM serial clock (SCL) / SPI serial port clock (SPC) I²C/MIPI I3CSM serial clock (SCL) / SPI serial port clock (SPC) Default: input without pull-up Default: input without pull-up Default: input without pull-up SDA I²C/MIPI I3CSM serial data (SDA) / SPI serial data inpu
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LSM6DSO Register mapping 8 Register mapping The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding addresses. Table 20.
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LSM6DSO Register mapping Name Type Register address Hex Binary Default Comment OUTY_H_G R 25 00100101 output OUTZ_L_G R 26 00100110 output OUTZ_H_G R 27 00100111 output OUTX_L_A R 28 00101000 output OUTX_H_A R 29 00101001 output OUTY_L_A R 2A 00101010 output OUTY_H_A R 2B 00101011 output OUTZ_L_A R 2C 00101100 output OUTZ_H_A R 2D 00101101 output RESERVED - 2E-34 EMB_FUNC_STATUS_MAINPAGE R 35 00110101 output FSM_STATUS_A_MAINPAGE R 36 00110110
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LSM6DSO Register mapping Name Type Register address Hex Binary Default Comment CTRL2_OIS R 71 01110001 00000000 RW (SPI2) CTRL3_OIS R 72 01110010 00000000 RW (SPI2) X_OFS_USR RW 73 01110011 00000000 Y_OFS_USR RW 74 01110100 00000000 Z_OFS_USR RW 75 01110101 00000000 RESERVED - 76-77 FIFO_DATA_OUT_TAG R 78 01111000 output FIFO_DATA_OUT_X_L R 79 01111001 output FIFO_DATA_OUT_X_H R 7A 01111010 output FIFO_DATA_OUT_Y_L R 7B 01111011 output FIFO_DATA_OUT_Y
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LSM6DSO Register description 9 Register description The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. The register addresses, made up of 7 bits, are used to identify them and to write the data through the serial interface. 9.1 FUNC_CFG_ACCESS (01h) Enable embedded functions register (r/w) Table 21. FUNC_CFG_ACCESS register FUNC_CFG_ ACCESS SHUB_REG ACCESS 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 1.
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LSM6DSO FIFO_CTRL1 (07h) 9.3 FIFO_CTRL1 (07h) FIFO control register 1 (r/w) Table 25. FIFO_CTRL1 register WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 Table 26. FIFO_CTRL1 register description FIFO watermark threshold, in conjunction with WTM8 in FIFO_CTRL2 (08h) WTM[7:0] 1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level. 9.
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LSM6DSO FIFO_CTRL3 (09h) 9.5 FIFO_CTRL3 (09h) FIFO control register 3 (r/w) Table 29. FIFO_CTRL3 register BDR_GY_3 BDR_GY_2 BDR_GY_1 BDR_GY_0 BDR_XL_3 BDR_XL_2 BDR_XL_1 BDR_XL_0 Table 30. FIFO_CTRL3 register description Selects Batching Data Rate (writing frequency in FIFO) for gyroscope data. (0000: Gyro not batched in FIFO (default); 0001: 12.5 Hz; 0010: 26 Hz; 0011: 52 Hz; 0100: 104 Hz; BDR_GY_[3:0] 0101: 208 Hz; 0110: 417 Hz; 0111: 833 Hz; 1000: 1667 Hz; 1001: 3333 Hz; 1010: 6667 Hz; 1011: 6.
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LSM6DSO FIFO_CTRL4 (0Ah) 9.6 FIFO_CTRL4 (0Ah) FIFO control register 4 (r/w) Table 31. FIFO_CTRL4 register DEC_TS_ BATCH_1 DEC_TS_ BATCH_0 ODR_T_ BATCH_1 ODR_T_ BATCH_0 0 FIFO_ MODE2 FIFO_ MODE1 FIFO_ MODE0 Table 32. FIFO_CTRL4 register description Selects decimation for timestamp batching in FIFO. Writing rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.
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LSM6DSO COUNTER_BDR_REG1 (0Bh) 9.7 COUNTER_BDR_REG1 (0Bh) Counter batch data rate register 1 (r/w) Table 33. COUNTER_BDR_REG1 register dataready_ pulsed RST_ COUNTER TRIG_ COUNTER _BDR _BDR 0 0 CNT_BDR_ TH_10 CNT_BDR_ TH_9 CNT_BDR_ TH_8 Table 34.
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LSM6DSO COUNTER_BDR_REG2 (0Ch) 9.8 COUNTER_BDR_REG2 (0Ch) Counter batch data rate register 2 (r/w) Table 35. COUNTER_BDR_REG2 register CNT_BDR_ TH_7 CNT_BDR_ TH_6 CNT_BDR_ TH_5 CNT_BDR_ TH_4 CNT_BDR_ TH_3 CNT_BDR_ TH_2 CNT_BDR_ TH_1 CNT_BDR_ TH_0 Table 36. COUNTER_BDR_REG2 register description In conjunction with CNT_BDR_TH_[10:8] in COUNTER_BDR_REG1 (0Bh), sets the threshold for the CNT_BDR_TH_[7:0] internal counter of batching events.
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LSM6DSO INT2_CTRL (0Eh) 9.10 INT2_CTRL (0Eh) INT2 pin control register (r/w) Each bit in this register enables a signal to be carried out on INT2 when the MIPI I3CSM dynamic address in not assigned (I²C or SPI is used). Some bits can be also used to trigger an IBI when the MIPI I3CSM interface is used. The output of the pin will be the OR combination of the signals selected here and in MD2_CFG (5Fh). Table 39.
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LSM6DSO CTRL1_XL (10h) 9.12 CTRL1_XL (10h) Accelerometer control register 1 (r/w) Table 42. CTRL1_XL register ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0 FS1_XL FS0_XL LPF2_XL_EN 0 Table 43.
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LSM6DSO CTRL2_G (11h) 9.13 CTRL2_G (11h) Gyroscope control register 2 (r/w) Table 46. CTRL2_G register ODR_G3 ODR_G2 ODR_G1 ODR_G0 FS1_G FS0_G FS_125 0 Table 47. CTRL2_G register description Gyroscope output data rate selection.
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LSM6DSO CTRL3_C (12h) 9.14 CTRL3_C (12h) Control register 3 (r/w) Table 49. CTRL3_C register BOOT BDU H_LACTIVE PP_OD SIM IF_INC 0 SW_RESET Table 50. CTRL3_C register description Reboots memory content. Default value: 0 BOOT (0: normal mode; 1: reboot memory content) This bit is automatically cleared. Block Data Update. Default value: 0 BDU (0: continuous update; 1: output registers are not updated until MSB and LSB have been read) H_LACTIVE PP_OD SIM IF_INC Interrupt activation level.
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LSM6DSO CTRL4_C (13h) 9.15 CTRL4_C (13h) Control register 4 (r/w) Table 51. CTRL4_C register 0 SLEEP_G INT2_on _INT1 0 DRDY_MASK I2C_disable LPF1_ SEL_G 0 Table 52. CTRL4_C register description SLEEP_G Enables gyroscope Sleep mode. Default value:0 (0: disabled; 1: enabled) All interrupt signals available on INT1 pin enable.
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LSM6DSO CTRL5_C (14h) 9.16 CTRL5_C (14h) Control register 5 (r/w) Table 53. CTRL5_C register XL_ULP_EN ROUNDING1 ROUNDING0 0 ST1_G ST0_G ST1_XL ST0_XL Table 54. CTRL5_C register description Accelerometer ultra-low-power mode enable. Default value: 0(1) XL_ULP_EN (0: Ultra-low-power mode disabled; 1: Ultra-low-power mode enabled) Circular burst-mode (rounding) read from the output registers.
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LSM6DSO CTRL6_C (15h) 9.17 CTRL6_C (15h) Control register 6 (r/w) Table 57. CTRL6_C register TRIG_EN LVL1_EN LVL2_EN XL_HM _MODE USR_ OFF_W FTYPE_2 FTYPE_1 FTYPE_0 Table 58. CTRL6_C register description TRIG_EN DEN data edge-sensitive trigger enable. Refer to Table 59. LVL1_EN DEN data level-sensitive trigger enable. Refer to Table 59. LVL2_EN DEN level-sensitive latched enable. Refer toTable 59. High-performance operating mode disable for accelerometer.
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LSM6DSO CTRL7_G (16h) 9.18 CTRL7_G (16h) Control register 7 (r/w) Table 61. CTRL7_G register G_HM_ MODE HP_EN_G HPM1_G HPM0_G 0(1) OIS_ON_EN USR_OFF _ON_OUT OIS_ON 1. This bit must be set to '0' for the correct operation of the device. Table 62. CTRL7_G register description Disables high-performance operating mode for gyroscope.
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LSM6DSO CTRL8_XL (17h) 9.19 CTRL8_XL (17h) Control register 8 (r/w) Table 63. CTRL8_XL register HPCF_XL_2 HPCF_XL_1 HP_REF_ MODE_XL HPCF_XL_0 FASTSETTL_ MODE_XL HP_SLOPE_ XL_EN XL_FS_ MODE LOW_PASS_ ON_6D Table 64. CTRL8_XL register description HPCF_XL_[2:0] Accelerometer LPF2 and HP filter configuration and cutoff setting. Refer to Table 65. Enables accelerometer high-pass filter reference mode (valid for high-pass path - HP_SLOPE_XL_EN bit must be ‘1’).
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LSM6DSO CTRL8_XL (17h) HP_SLOPE_ Filter type LPF2_XL_EN XL_EN High pass 1 HPCF_XL_[2:0] Bandwidth 000 SLOPE (ODR/4) 001 ODR/10 010 ODR/20 011 ODR/45 100 ODR/100 101 ODR/200 110 ODR/400 111 ODR/800 - Figure 24.
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LSM6DSO CTRL9_XL (18h) 9.20 CTRL9_XL (18h) Control register 9 (r/w) Table 66. CTRL9_XL register DEN_X DEN_Y DEN_Z DEN_XL_G DEN_XL_EN DEN_LH I3C_disable 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 67. CTRL9_XL register description DEN_X DEN_Y DEN_Z DEN value stored in LSB of X-axis. Default value: 1 (0: DEN not stored in X-axis LSB; 1: DEN stored in X-axis LSB) DEN value stored in LSB of Y-axis.
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LSM6DSO CTRL10_C (19h) 9.21 CTRL10_C (19h) Control register 10 (r/w) Table 68. CTRL10_C register 0 TIMESTAMP _EN 0 0 0 0 0 0 Table 69. CTRL10_C register description Enables timestamp counter. default value: 0 TIMESTAMP_EN (0: disabled; 1: enabled) The counter is readable in TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h). 9.22 ALL_INT_SRC (1Ah) Source register for all interrupts (r) Table 70.
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LSM6DSO WAKE_UP_SRC (1Bh) 9.23 WAKE_UP_SRC (1Bh) Wake-up interrupt source register (r) Table 72. WAKE_UP_SRC register 0 SLEEP_ CHANGE_IA FF_IA SLEEP_ STATE WU_IA X_WU Y_WU Z_WU Table 73. WAKE_UP_SRC register description SLEEP_ CHANGE_IA FF_IA SLEEP_STATE WU_IA X_WU Y_WU Z_WU DS12140 - Rev 2 Detects change event in activity/inactivity status. Default value: 0 (0: change status not detected; 1: change status detected) Free-fall event detection status.
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LSM6DSO TAP_SRC (1Ch) 9.24 TAP_SRC (1Ch) Tap source register (r) Table 74. TAP_SRC register 0 TAP_IA SINGLE_ TAP DOUBLE_ TAP TAP_SIGN X_TAP Y_TAP Z_TAP Table 75. TAP_SRC register description TAP_IA SINGLE_TAP DOUBLE_TAP Tap event detection status. Default: 0 (0: tap event not detected; 1: tap event detected) Single-tap event status. Default value: 0 (0: single tap event not detected; 1: single tap event detected) Double-tap event detection status.
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LSM6DSO D6D_SRC (1Dh) 9.25 D6D_SRC (1Dh) Portrait, landscape, face-up and face-down source register (r) Table 76. D6D_SRC register DEN_DRDY D6D_IA ZH ZL YH YL XH XL Table 77. D6D_SRC register description DEN_DRDY D6D_IA ZH ZL YH YL XH XL DEN data-ready signal. It is set high when data output is related to the data coming from a DEN active condition.(1) Interrupt active for change position portrait, landscape, face-up, face-down.
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LSM6DSO STATUS_REG (1Eh) / STATUS_SPIAux (1Eh) 9.26 STATUS_REG (1Eh) / STATUS_SPIAux (1Eh) The STATUS_REG register is read by the primary interface SPI/I²C & MIPI I3CSM (r). Table 78. STATUS_REG register 0 0 0 0 0 TDA GDA XLDA GDA XLDA Table 79. STATUS_REG register description Temperature new data available. Default: 0 TDA (0: no set of data is available at temperature sensor output; 1: a new set of data is available at temperature sensor output) Gyroscope new data available.
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LSM6DSO OUT_TEMP_L (20h), OUT_TEMP_H (21h) 9.27 OUT_TEMP_L (20h), OUT_TEMP_H (21h) Temperature data output register (r). L and H registers together express a 16-bit word in two’s complement. Table 82. OUT_TEMP_L register Temp7 Temp6 Temp5 Temp4 Temp3 Temp2 Temp1 Temp0 Temp10 Temp9 Temp8 Table 83. OUT_TEMP_H register Temp15 Temp14 Temp13 Temp12 Temp11 Table 84. OUT_TEMP register description Temp[15:0] 9.
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LSM6DSO OUTY_L_G (24h) and OUTY_H_G (25h) 9.29 OUTY_L_G (24h) and OUTY_H_G (25h) Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement. If this register is read by the primary interface, data are according to the full scale and ODR settings (CTRL2_G (11h)) of the gyro user interface. If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of the OIS gyro. Table 88.
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LSM6DSO OUTX_L_A (28h) and OUTX_H_A (29h) 9.31 OUTX_L_A (28h) and OUTX_H_A (29h) Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s complement. If this register is read by the primary interface, data are according to the full-scale and ODR settings (CTRL1_XL (10h)) of the accelerometer user interface. If this register is read by the auxiliary interface, data are according to the full-scale and ODR (6.66 kHz) settings of the OIS (CTRL3_OIS (72h)).
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LSM6DSO OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) 9.33 OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s complement. If this register is read by the primary interface, data are according to the full-scale and ODR settings (CTRL1_XL (10h)) of the accelerometer user interface. If this register is read by the auxiliary interface, data are according to the full-scale and ODR (6.66 kHz) settings of the OIS (CTRL3_OIS (72h)).
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LSM6DSO FSM_STATUS_A_MAINPAGE (36h) 9.35 FSM_STATUS_A_MAINPAGE (36h) Finite State Machine status register (r) Table 105. FSM_STATUS_A_MAINPAGE register IS_FSM8 IS_FSM7 IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1 Table 106. FSM_STATUS_A_MAINPAGE register description IS_FSM8 IS_FSM7 IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1 DS12140 - Rev 2 Interrupt status bit for FSM8 interrupt event. (1: interrupt detected; 0: no interrupt) Interrupt status bit for FSM7 interrupt event.
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LSM6DSO FSM_STATUS_B_MAINPAGE (37h) 9.36 FSM_STATUS_B_MAINPAGE (37h) Finite State Machine status register (r) Table 107. FSM_STATUS_B_MAINPAGE register IS_FSM16 IS_FSM15 IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9 Table 108. FSM_STATUS_B_MAINPAGE register description Interrupt status bit for FSM16 interrupt event. IS_FSM16 (1: interrupt detected; 0: no interrupt) Interrupt status bit for FSM15 interrupt event.
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LSM6DSO FIFO_STATUS1 (3Ah) 9.38 FIFO_STATUS1 (3Ah) FIFO status register 1 (r) Table 111. FIFO_STATUS1 register DIFF_ FIFO_7 DIFF_ FIFO_6 DIFF_ FIFO_5 DIFF_ FIFO_4 DIFF_ FIFO_3 DIFF_ FIFO_2 DIFF_ FIFO_1 DIFF_ FIFO_0 DIFF_ FIFO_9 DIFF_ FIFO_8 Table 112. FIFO_STATUS1 register description Number of unread sensor data (TAG + 6 bytes) stored in FIFO DIFF_FIFO_[7:0] 9.39 In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh). FIFO_STATUS2 (3Bh) FIFO status register 2 (r) Table 113.
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LSM6DSO TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) 9.40 TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) Timestamp first data output register (r). The value is expressed as a 32-bit word and the bit resolution is 25 µs. Table 115. TIMESTAMP output registers D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 116.
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LSM6DSO TAP_CFG0 (56h) 9.41 TAP_CFG0 (56h) Activity/inactivity functions, configuration of filtering, and tap recognition functions (r/w) Table 117. TAP_CFG0 register 0 INT_CLR_ ON_READ SLEEP_ STATUS_ ON_INT SLOPE_FDS TAP_X_EN TAP_Y_EN TAP_Z_EN LIR Table 118. TAP_CFG0 register description This bit allows immediately clearing the latched interrupts of an event detection upon the read of the corresponding status register. It must be set to 1 together with LIR.
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LSM6DSO TAP_CFG1 (57h) 9.42 TAP_CFG1 (57h) Tap configuration register (r/w) Table 119. TAP_CFG1 register TAP_ PRIORITY_2 TAP_ PRIORITY_1 TAP_ PRIORITY_0 TAP_THS_X_4 TAP_THS_X_3 TAP_THS_X_2 TAP_THS_X_1 TAP_THS_X_0 Table 120. TAP_CFG1 register description TAP_PRIORITY_[2:0] Selection of axis priority for TAP detection (see Table 121) X-axis tap recognition threshold. Default value: 0 TAP_THS_X_[4:0] 1 LSB = FS_XL / (25) Table 121. TAP priority decoding 9.43 TAP_PRIORITY_[2:0] Max.
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LSM6DSO TAP_THS_6D (59h) 9.44 TAP_THS_6D (59h) Portrait/landscape position and tap function threshold register (r/w). Table 124. TAP_THS_6D register D4D_EN SIXD_THS1 SIXD_THS0 TAP_ THS_Z_4 TAP_ THS_Z_3 TAP_ THS_Z_2 TAP_ THS_Z_1 TAP_ THS_Z_0 Table 125. TAP_THS_6D register description 4D orientation detection enable. Z-axis position detection is disabled. D4D_EN Default value: 0 (0: enabled; 1: disabled) SIXD_THS[1:0] TAP_THS_Z_[4:0] Threshold for 4D/6D function.
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LSM6DSO INT_DUR2 (5Ah) 9.45 INT_DUR2 (5Ah) Tap recognition function setting register (r/w). Table 127. INT_DUR2 register DUR3 DUR2 DUR1 DUR0 QUIET1 QUIET0 SHOCK1 SHOCK0 Table 128. INT_DUR2 register description Duration of maximum time gap for double tap recognition. Default: 0000 DUR[3:0] When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event.
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LSM6DSO WAKE_UP_DUR (5Ch) 9.47 WAKE_UP_DUR (5Ch) Free-fall, wakeup and sleep mode functions duration setting register (r/w) Table 131. WAKE_UP_DUR register FF_DUR5 WAKE_DUR1 WAKE_DUR0 WAKE_THS_ W SLEEP_DUR 3 SLEEP_DUR 2 SLEEP_DUR 1 SLEEP_DUR 0 Table 132. WAKE_UP_DUR register description Free fall duration event. Default: 0 FF_DUR5 For the complete configuration of the free-fall duration, refer to FF_DUR[4:0] in FREE_FALL (5Dh) configuration.
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LSM6DSO FREE_FALL (5Dh) 9.48 FREE_FALL (5Dh) Free-fall function duration setting register (r/w) Table 133. FREE_FALL register FF_DUR4 FF_DUR3 FF_DUR2 FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0 Table 134. FREE_FALL register description Free-fall duration event. Default: 0 FF_DUR[4:0] For the complete configuration of the free fall duration, refer to FF_DUR5 in WAKE_UP_DUR (5Ch) configuration FF_THS[2:0] Free fall threshold setting. Default: 000 For details refer to Table 135. Table 135.
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LSM6DSO MD1_CFG (5Eh) 9.49 MD1_CFG (5Eh) Functions routing on INT1 register (r/w) Table 136. MD1_CFG register INT1_ INT1_ SLEEP_ CHANGE SINGLE_ TAP INT1_ INT1_WU INT1_FF DOUBLE_ TAP INT1_6D INT1_ EMB_FUNC INT1_ SHUB Table 137. MD1_CFG register description Routing of activity/inactivity recognition event on INT1.
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LSM6DSO MD2_CFG (5Fh) 9.50 MD2_CFG (5Fh) Functions routing on INT2 register (r/w) Table 138. MD2_CFG register INT2_ SLEEP_ CHANGE INT2_ INT2_ SINGLE_ TAP INT2_WU INT2_FF DOUBLE_ INT2_ INT2_6D TAP EMB_ INT2_ TIMESTAMP FUNC Table 139. MD2_CFG register description Routing of activity/inactivity recognition event on INT2.
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LSM6DSO I3C_BUS_AVB (62h) 9.51 I3C_BUS_AVB (62h) I3C_BUS_AVB register (r/w) Table 140. I3C_BUS_AVB register 0(1) 0(1) 0(1) I3C_Bus_Avb I3C_Bus_Avb _Sel1 _Sel0 0(1) 0(1) PD_DIS_ INT1 1. This bit must be set to '0' for the correct operation of the device. Table 141. I3C_BUS_AVB register description This bit allows disabling the INT1 pull-down.
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LSM6DSO INT_OIS (6Fh) 9.53 INT_OIS (6Fh) OIS interrupt configuration register and accelerometer self-test enable setting. Primary interface for read-only (r); only Aux SPI can write to this register (r/w). Table 144. INT_OIS register INT2_ DRDY_OIS LVL2_OIS DEN_LH_OIS - - 0 ST1_XL_OIS ST0_XL_OIS Table 145. INT_OIS register description INT2_DRDY_OIS Enables OIS chain DRDY on INT2 pin. This setting has priority over all other INT2 settings.
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LSM6DSO CTRL1_OIS (70h) 9.54 CTRL1_OIS (70h) OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w). Table 146. CTRL1_OIS register 0 LVL1_OIS SIM_OIS Mode4_EN FS1_G_ OIS FS0_G_ OIS FS_125_ OIS OIS_EN_ SPI2 Table 147. CTRL1_OIS register description LVL1_OIS Enables OIS data level-sensitive trigger SPI2 3- or 4-wire interface. Default value: 0 SIM_OIS (0: 4-wire SPI2; 1: 3-wire SPI2) Mode4_EN Enables accelerometer OIS chain.
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LSM6DSO CTRL2_OIS (71h) 9.55 CTRL2_OIS (71h) OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w). Table 149. CTRL2_OIS register - - HPM1_OIS HPM0_OIS 0 FTYPE_1 _OIS FTYPE_0 _OIS HP_EN_OIS Table 150. CTRL2_OIS register description Selects gyroscope OIS chain digital high-pass filter cutoff. Default value: 00 (00: 16 mHz; HPM[1:0]_OIS 01: 65 mHz; 10: 260 mHz; 11: 1.04 Hz) FTYPE_[1:0]_OIS Selects gyroscope digital LPF1 filter bandwidth.
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LSM6DSO CTRL3_OIS (72h) 9.56 CTRL3_OIS (72h) OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w). Table 152. CTRL3_OIS register FS1_XL_ OIS FS0_XL_ OIS FILTER_XL_ FILTER_XL_ FILTER_XL_ CONF_OIS_2 CONF_OIS_1 CONF_OIS_0 ST1_OIS ST_OIS_ CLAMPDIS ST0_OIS Table 153. CTRL3_OIS register description FS[1:0]_XL_OIS Selects accelerometer OIS channel full-scale. See Table 154. FILTER_XL_ CONF_OIS_[2:0] Selects accelerometer OIS channel bandwidth.
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LSM6DSO X_OFS_USR (73h) FILTER_XL_CONF_OIS[2:0] Typ. overall bandwidth [Hz] Typ. overall phase [°] 110 8.30 -26.7 @ 4 Hz 111 4.14 -26.2 @ 2 Hz Table 156. Self-test nominal output variation 9.57 Full scale Ouput variation [dps] 2000 400 1000 200 500 100 250 50 125 25 X_OFS_USR (73h) Accelerometer X-axis user offset correction (r/w). The offset value set in the X_OFS_USR offset register is internally subtracted from the acceleration value measured on the X-axis. Table 157.
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LSM6DSO Z_OFS_USR (75h) 9.59 Z_OFS_USR (75h) Accelerometer Z-axis user offset correction (r/w). The offset value set in the Z_OFS_USR offset register is internally subtracted from the acceleration value measured on the Z-axis. Table 161. Z_OFS_USR register Z_OFS_ USR_7 Z_OFS_ USR_6 Z_OFS_ USR_5 Z_OFS_ USR_4 Z_OFS_ USR_3 Z_OFS_ USR_2 Z_OFS_ USR_1 Z_OFS_ USR_0 Table 162. Z_OFS_USR register description Z_OFS_USR_[7:0] 9.
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LSM6DSO FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) 9.61 TAG_SENSOR_[4:0] Sensor name 0x0F Sensor Hub Slave 1 0x10 Sensor Hub Slave 2 0x11 Sensor Hub Slave 3 0x12 Step Counter 0x19 Sensor Hub Nack FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) FIFO data output X (r) Table 166. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 167.
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LSM6DSO Embedded functions register mapping 10 Embedded functions register mapping The table given below provides a list of the registers for the embedded functions available in the device and the corresponding addresses. Embedded functions registers are accessible when FUNC_CFG_EN is set to '1' in FUNC_CFG_ACCESS (01h). Table 172.
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LSM6DSO Embedded functions register mapping Name Type Register address Hex Binary Default FSM_OUTS11 r 56 01010110 output FSM_OUTS12 r 57 01010111 output FSM_OUTS13 r 58 01011000 output FSM_OUTS14 r 59 01011001 output FSM_OUTS15 r 5A 01011010 output FSM_OUTS16 r 5B 01011011 output 5E 01011110 r/w 5F 01011111 01001011 STEP_COUNTER_L r 62 01100010 output STEP_COUNTER_H r 63 01100011 output EMB_FUNC_SRC r/w 64 01100100 output EMB_FUNC_INIT_A r/w 66 01
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LSM6DSO Embedded functions register description 11 Embedded functions register description 11.1 PAGE_SEL (02h) Enable advanced features dedicated page (r/w) Table 173. PAGE_SEL register PAGE_SEL3 PAGE_SEL2 PAGE_SEL1 0(1) PAGE_SEL0 0(1) 0(1) 1(2) 0(1) 0(1) 1. This bit must be set to '0' for the correct operation of the device. 2. This bit must be set to '1' for the correct operation of the device. Table 174.
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LSM6DSO EMB_FUNC_EN_B (05h) 11.3 EMB_FUNC_EN_B (05h) Embedded functions enable register (r/w) Table 177. EMB_FUNC_EN_B register 0(1) 0(1) PEDO_ ADV_EN 0(1) FIFO_ COMPR_EN 0(1) 0(1) FSM_EN 1. This bit must be set to '0' for the correct operation of the device. Table 178. EMB_FUNC_EN_B register description Enable pedometer false-positive rejection block and advanced detection feature block.
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LSM6DSO PAGE_VALUE (09h) 11.5 PAGE_VALUE (09h) Page value register (r/w) Table 181. PAGE_VALUE register PAGE_ VALUE7 PAGE_ VALUE6 PAGE_ VALUE5 PAGE_ VALUE4 PAGE_ VALUE3 PAGE_ VALUE2 PAGE_ VALUE1 PAGE_ VALUE0 Table 182. PAGE_VALUE register description These bits are used to write (if the bit PAGE_WRITE = 1 in register PAGE_RW (17h)) or read (if the bit PAGE_VALUE[7:0] PAGE_READ = 1 in register PAGE_RW (17h)) the data at the address PAGE_ADDR[7:0] of the selected advanced features page. 11.
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LSM6DSO FSM_INT1_A (0Bh) 11.7 FSM_INT1_A (0Bh) INT1 pin control register (r/w) Each bit in this register enables a signal to be carried through INT1. The pin's output will supply the OR combination of the selected signals. Table 185. FSM_INT1_A register INT1_ FSM8 INT1_ FSM7 INT1_ FSM6 INT1_ FSM5 INT1_ FSM4 INT1_ FSM3 INT1_ FSM2 INT1_ FSM1 Table 186.
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LSM6DSO FSM_INT1_B (0Ch) 11.8 FSM_INT1_B (0Ch) INT1 pin control register (r/w) Each bit in this register enables a signal to be carried through INT1. The pin's output will supply the OR combination of the selected signals. Table 187. FSM_INT1_B register INT1_ FSM16 INT1_ FSM15 INT1_ FSM14 INT1_ FSM13 INT1_ FSM12 INT1_ FSM11 INT1_ FSM10 INT1_ FSM9 Table 188.
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LSM6DSO EMB_FUNC_INT2 (0Eh) 11.9 EMB_FUNC_INT2 (0Eh) INT2 pin control register (r/w) Each bit in this register enables a signal to be carried through INT2. The pin's output will supply the OR combination of the selected signals. Table 189. EMB_FUNC_INT2 register INT2_ FSM_LC 0(1) INT2_ SIG_MOT INT2_TILT INT2_STEP_ DETECTOR 0(1) 0(1) 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 190.
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LSM6DSO FSM_INT2_A (0Fh) 11.10 FSM_INT2_A (0Fh) INT2 pin control register (r/w) Each bit in this register enables a signal to be carried through INT2. The pin's output will supply the OR combination of the selected signals. Table 191. FSM_INT2_A register INT2_ FSM8 INT2_ FSM7 INT2_ FSM6 INT2_ FSM5 INT2_ FSM4 INT2_ FSM3 INT2_ FSM2 INT2_ FSM1 Table 192.
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LSM6DSO FSM_INT2_B (10h) 11.11 FSM_INT2_B (10h) INT2 pin control register (r/w) Each bit in this register enables a signal to be carried through INT2. The pin's output will supply the OR combination of the selected signals. Table 193. FSM_INT2_B register INT2_ FSM16 INT2_ FSM15 INT2_ FSM14 INT2_ FSM13 INT2_ FSM12 INT2_ FSM11 INT2_ FSM10 INT2_ FSM9 Table 194.
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LSM6DSO EMB_FUNC_STATUS (12h) 11.12 EMB_FUNC_STATUS (12h) Embedded function status register (r) Table 195. EMB_FUNC_STATUS register IS_ FSM_LC 0 IS_ SIGMOT IS_ TILT IS_ STEP_DET 0 0 0 Table 196. EMB_FUNC_STATUS register description IS_FSM_LC IS_SIGMOT IS_TILT IS_STEP_DET DS12140 - Rev 2 Interrupt status bit for FSM long counter timeout interrupt event.
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LSM6DSO FSM_STATUS_A (13h) 11.13 FSM_STATUS_A (13h) Finite State Machine status register (r) Table 197. FSM_STATUS_A register IS_FSM8 IS_FSM7 IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1 Table 198. FSM_STATUS_A register description IS_FSM8 IS_FSM7 IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1 DS12140 - Rev 2 Interrupt status bit for FSM8 interrupt event. (1: interrupt detected; 0: no interrupt) Interrupt status bit for FSM7 interrupt event.
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LSM6DSO FSM_STATUS_B (14h) 11.14 FSM_STATUS_B (14h) Finite State Machine status register (r) Table 199. FSM_STATUS_B register IS_FSM16 IS_FSM15 IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9 Table 200. FSM_STATUS_B register description IS_FSM16 IS_FSM15 IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9 DS12140 - Rev 2 Interrupt status bit for FSM16 interrupt event. (1: interrupt detected; 0: no interrupt) Interrupt status bit for FSM15 interrupt event.
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LSM6DSO PAGE_RW (17h) 11.15 PAGE_RW (17h) Enable read and write mode of advanced features dedicated page (r/w) Table 201. PAGE_RW register EMB_ FUNC_LIR PAGE_ WRITE PAGE_ READ 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 202. PAGE_RW register description Latched Interrupt mode for embedded functions.
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LSM6DSO FSM_ENABLE_A (46h) 11.17 FSM_ENABLE_A (46h) FSM enable register (r/w) Table 205. FSM_ENABLE_A register FSM8_EN FSM7_EN FSM6_EN FSM5_EN FSM4_EN FSM3_EN FSM2_EN FSM1_EN FSM10_EN FSM9_EN Table 206. FSM_ENABLE_A register description 11.18 FSM8_EN FSM8 enable. Default value: 0 (0: FSM8 disabled; 1: FSM8 enabled) FSM7_EN FSM7 enable. Default value: 0 (0: FSM7 disabled; 1: FSM7 enabled) FSM6_EN FSM6 enable. Default value: 0 (0: FSM6 disabled; 1: FSM6 enabled) FSM5_EN FSM5 enable.
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LSM6DSO FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h) 11.19 FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h) FSM long counter status register (r/w) Long counter value is an unsigned integer value (16-bit format); this value can be reset using the LC_CLEAR bit in FSM_LONG_COUNTER_CLEAR (4Ah) register. Table 209. FSM_LONG_COUNTER_L register FSM_LC_7 FSM_LC_6 FSM_LC_5 FSM_LC_4 FSM_LC_3 FSM_LC_2 FSM_LC_1 FSM_LC_0 FSM_LC_9 FSM_LC_8 FSM_LC_ CLEARED FSM_LC_ CLEAR Table 210.
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LSM6DSO FSM_OUTS1 (4Ch) 11.21 FSM_OUTS1 (4Ch) FSM1 output register (r) Table 215. FSM_OUTS1 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 216. FSM_OUTS1 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM1 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM1 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM1 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS2 (4Dh) 11.22 FSM_OUTS2 (4Dh) FSM2 output register (r) Table 217. FSM_OUTS2 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 218. FSM_OUTS2 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM2 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM2 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM2 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS3 (4Eh) 11.23 FSM_OUTS3 (4Eh) FSM3 output register (r) Table 219. FSM_OUTS3 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 220. FSM_OUTS3 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM3 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM3 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM3 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS4 (4Fh) 11.24 FSM_OUTS4 (4Fh) FSM4 output register (r) Table 221. FSM_OUTS4 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 222. FSM_OUTS4 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM4 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM4 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM4 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS5 (50h) 11.25 FSM_OUTS5 (50h) FSM5 output register (r) Table 223. FSM_OUTS5 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 224. FSM_OUTS5 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM5 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM5 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM5 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS6 (51h) 11.26 FSM_OUTS6 (51h) FSM6 output register (r) Table 225. FSM_OUTS6 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 226. FSM_OUTS6 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM6 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM6 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM6 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS7 (52h) 11.27 FSM_OUTS7 (52h) FSM7 output register (r) Table 227. FSM_OUTS7 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 228. FSM_OUTS7 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM7 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM7 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM7 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS8 (53h) 11.28 FSM_OUTS8 (53h) FSM8 output register (r) Table 229. FSM_OUTS8 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 230. FSM_OUTS8 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM8 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM8 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM8 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS9 (54h) 11.29 FSM_OUTS9 (54h) FSM9 output register (r) Table 231. FSM_OUTS9 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 232. FSM_OUTS9 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM9 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM9 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM9 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS10 (55h) 11.30 FSM_OUTS10 (55h) FSM10 output register (r) Table 233. FSM_OUTS10 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 234. FSM_OUTS10 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM10 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM10 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM10 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS11 (56h) 11.31 FSM_OUTS11 (56h) FSM11 output register (r) Table 235. FSM_OUTS11 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 236. FSM_OUTS11 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM11 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM11 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM11 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS12 (57h) 11.32 FSM_OUTS12 (57h) FSM12 output register (r) Table 237. FSM_OUTS12 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 238. FSM_OUTS12 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM12 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM12 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM12 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS13 (58h) 11.33 FSM_OUTS13 (58h) FSM13 output register (r) Table 239. FSM_OUTS13 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 240. FSM_OUTS13 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM13 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM13 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM13 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS14 (59h) 11.34 FSM_OUTS14 (59h) FSM14 output register (r) Table 241. FSM_OUTS14 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 242. FSM_OUTS14 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM14 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM14 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM14 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS15 (5Ah) 11.35 FSM_OUTS15 (5Ah) FSM15 output register (r) Table 243. FSM_OUTS15 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 244. FSM_OUTS15 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM15 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM15 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM15 output: positive event detected on the Y-axis.
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LSM6DSO FSM_OUTS16 (5Bh) 11.36 FSM_OUTS16 (5Bh) FSM16 output register (r) Table 245. FSM_OUTS16 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 246. FSM_OUTS16 register description P_X N_X P_Y N_Y P_Z N_Z P_V N_V DS12140 - Rev 2 FSM16 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) FSM16 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) FSM16 output: positive event detected on the Y-axis.
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LSM6DSO EMB_FUNC_ODR_CFG_B (5Fh) 11.37 EMB_FUNC_ODR_CFG_B (5Fh) Finite State Machine output data rate configuration register (r/w) Table 247. EMB_FUNC_ODR_CFG_B register 0(1) 1(2) 0(1) FSM_ODR1 FSM_ODR0 0(1) 1(2) 1(2) STEP_1 STEP_0 STEP_9 STEP_8 1. This bit must be set to '0' for the correct operation of the device. 2. This bit must be set to '1' for the correct operation of the device. Table 248. EMB_FUNC_ODR_CFG_B register description Finite State Machine ODR configuration: (00: 12.
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LSM6DSO EMB_FUNC_SRC (64h) 11.39 EMB_FUNC_SRC (64h) Embedded function source register (r/w) Table 253. EMB_FUNC_SRC register STEP_ PEDO_RST _STEP STEP_ DETECTED 0 COUNT_ STEP_ OVERFLOW STEPCOUNT ER_BIT_SET 0 0 DELTA_IA Table 254. EMB_FUNC_SRC register description Reset pedometer step counter. Read/write bit. PEDO_RST_STEP (0: disabled; 1: enabled) Step detector event detection status. Read-only bit.
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LSM6DSO EMB_FUNC_INIT_B (67h) 11.41 EMB_FUNC_INIT_B (67h) Embedded functions initialization register (r/w) Table 257. EMB_FUNC_INIT_B register 0(1) 0(1) 0(1) 0(1) FIFO_ COMPR_INIT 0(1) 0(1) FSM_INIT 1. This bit must be set to '0' for the correct operation of the device. Table 258. EMB_FUNC_INIT_B register description DS12140 - Rev 2 FIFO_COMPR_INIT FIFO compression feature initialization request. Default value: 0 FSM_INIT FSM initialization request.
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LSM6DSO Embedded advanced features pages 12 Embedded advanced features pages The table given below provides a list of the registers for the embedded advanced features page 0. These registers are accessible when PAGE_SEL[3:0] are set to 0000 in PAGE_SEL (02h). Table 259.
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LSM6DSO Embedded advanced features pages Name Type Register address Hex Binary Default FSM_START_ADD_L r/w 7E 01111110 00000000 FSM_START_ADD_H r/w 7F 01111111 00000000 PEDO_CMD_REG r/w 83 10000011 00000000 PEDO_DEB_STEPS_CONF r/w 84 10000100 00001010 PEDO_SC_DELTAT_L r/w D0 11010000 00000000 PEDO_SC_DELTAT_H r/w D1 11010001 00000000 Comment Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.
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LSM6DSO Embedded advanced features register description 13 Embedded advanced features register description 13.1 Page 0 - Embedded advanced features registers 13.1.1 MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh) External magnetometer sensitivity value register (r/w) for the Finite State Machine This register corresponds to the LSB-to-gauss conversion value of the external magnetometer sensor.
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LSM6DSO Page 0 - Embedded advanced features registers 13.1.2 MAG_OFFX_L (C0h) and MAG_OFFX_H (C1h) Offset for X-axis hard-iron compensation register (r/w) The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 265. MAG_OFFX_L register MAG_OFFX_7 MAG_OFFX_6 MAG_OFFX_5 MAG_OFFX_4 MAG_OFFX_3 MAG_OFFX_2 MAG_OFFX_1 MAG_OFFX_0 Table 266.
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LSM6DSO Page 0 - Embedded advanced features registers 13.1.4 MAG_OFFZ_L (C4h) and MAG_OFFZ_H (C5h) Offset for Z-axis hard-iron compensation register (r/w) The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 273. MAG_OFFZ_L register MAG_OFFZ_7 MAG_OFFZ_6 MAG_OFFZ_5 MAG_OFFZ_4 MAG_OFFZ_3 MAG_OFFZ_2 MAG_OFFZ_1 MAG_OFFZ_0 Table 274.
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LSM6DSO Page 0 - Embedded advanced features registers 13.1.6 MAG_SI_XY_L (C8h) and MAG_SI_XY_H (C9h) Soft-iron (3x3 symmetric) matrix correction register (r/w) The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 281. MAG_SI_XY_L register MAG_SI_XY_7 MAG_SI_XY_6 MAG_SI_XY_5 MAG_SI_XY_4 MAG_SI_XY_3 MAG_SI_XY_2 MAG_SI_XY_1 MAG_SI_XY_0 Table 282.
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LSM6DSO Page 0 - Embedded advanced features registers 13.1.8 MAG_SI_YY_L (CCh) and MAG_SI_YY_H (CDh) Soft-iron (3x3 symmetric) matrix correction register (r/w) The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 289. MAG_SI_YY_L register MAG_SI_YY_7 MAG_SI_YY_6 MAG_SI_YY_5 MAG_SI_YY_4 MAG_SI_YY_3 MAG_SI_YY_2 MAG_SI_YY_1 MAG_SI_YY_0 Table 290.
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LSM6DSO Page 0 - Embedded advanced features registers 13.1.10 MAG_SI_ZZ_L (D0h) and MAG_SI_ZZ_H (D1h) Soft-iron (3x3 symmetric) matrix correction register (r/w) The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 297. MAG_SI_ZZ_L register MAG_SI_ZZ_7 MAG_SI_ZZ_6 MAG_SI_ZZ_5 MAG_SI_ZZ_4 MAG_SI_ZZ_3 MAG_SI_ZZ_2 MAG_SI_ZZ_1 MAG_SI_ZZ_0 Table 298.
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LSM6DSO Page 0 - Embedded advanced features registers 13.1.11 MAG_CFG_A (D4h) External magnetometer coordinates (Y and Z axes) rotation register (r/w) Table 301. MAG_CFG_A register 0(1) MAG_Y_ AXIS2 MAG_Y_ AXIS1 MAG_Y_ AXIS0 0(1) MAG_Z_ AXIS2 MAG_Z_ AXIS1 MAG_Z_ AXIS0 1. This bit must be set to ‘0’ for the correct operation of the device. Table 302.
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LSM6DSO Page 1 - Embedded advanced features registers 13.2 Page 1 - Embedded advanced features registers 13.2.1 FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh) FSM long counter timeout register (r/w) The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reaches this value, the FSM generates an interrupt. Table 305.
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LSM6DSO Page 1 - Embedded advanced features registers 13.2.3 FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh) FSM start address register (r/w). First available address is 0x033C. Table 311. FSM_START_ADD_L register FSM_ START7 FSM_ START6 FSM_ START5 FSM_ START4 FSM_ START3 FSM_ START2 FSM_ START1 FSM_ START0 FSM_ START9 FSM_ START8 0(1) AD_ DET_EN Table 312. FSM_START_ADD_L register description FSM_START[7:0] FSM start address value (LSbyte). Default value: 00000000 Table 313.
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LSM6DSO Page 1 - Embedded advanced features registers 13.2.5 PEDO_DEB_STEPS_CONF (84h) Pedometer debounce configuration register (r/w) Table 317. PEDO_DEB_STEPS_CONF register DEB_ STEP7 DEB_ STEP6 DEB_ STEP5 DEB_ STEP4 DEB_ STEP3 DEB_ STEP2 DEB_ STEP1 DEB_ STEP0 Table 318. PEDO_DEB_STEPS_CONF register description DEB_STEP[7:0] 13.2.6 Debounce threshold. Minimum number of steps to increment the step counter (debounce).
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LSM6DSO Sensor hub register mapping 14 Sensor hub register mapping The table given below provides a list of the registers for the sensor hub functions available in the device and the corresponding addresses. The sensor hub registers are accessible when bit SHUB_REG_ACCESS is set to '1' in FUNC_CFG_ACCESS (01h). Table 322.
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LSM6DSO Sensor hub register mapping Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
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LSM6DSO Sensor hub register description 15 Sensor hub register description 15.1 SENSOR_HUB_1 (02h) Sensor hub output register (r) First byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 323. SENSOR_HUB_1 register Sensor Hub1_7 Sensor Hub1_6 Sensor Hub1_5 Sensor Hub1_4 Sensor Hub1_3 Sensor Hub1_2 Sensor Hub1_1 Sensor Hub1_0 Table 324.
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LSM6DSO SENSOR_HUB_4 (05h) 15.4 SENSOR_HUB_4 (05h) Sensor hub output register (r) Fourth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 329. SENSOR_HUB_4 register Sensor Hub4_7 Sensor Hub4_6 Sensor Hub4_5 Sensor Hub4_4 Sensor Hub4_3 Sensor Hub4_2 Sensor Hub4_1 Sensor Hub4_0 Table 330. SENSOR_HUB_4 register description SensorHub4[7:0] 15.
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LSM6DSO SENSOR_HUB_7 (08h) 15.7 SENSOR_HUB_7 (08h) Sensor hub output register (r) Seventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 335. SENSOR_HUB_7 register Sensor Hub7_7 Sensor Hub7_6 Sensor Hub7_5 Sensor Hub7_4 Sensor Hub7_3 Sensor Hub7_2 Sensor Hub7_1 Sensor Hub7_0 Table 336. SENSOR_HUB_7 register description SensorHub7[7:0] 15.
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LSM6DSO SENSOR_HUB_10 (0Bh) 15.10 SENSOR_HUB_10 (0Bh) Sensor hub output register (r) Tenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 341. SENSOR_HUB_10 register Sensor Hub10_7 Sensor Hub10_6 Sensor Hub10_5 Sensor Hub10_4 Sensor Hub10_3 Sensor Hub10_2 Sensor Hub10_1 Sensor Hub10_0 Table 342. SENSOR_HUB_10 register description SensorHub10[7:0] 15.
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LSM6DSO SENSOR_HUB_13 (0Eh) 15.13 SENSOR_HUB_13 (0Eh) Sensor hub output register (r) Thirteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 347. SENSOR_HUB_13 register Sensor Hub13_7 Sensor Hub13_6 Sensor Hub13_5 Sensor Hub13_4 Sensor Hub13_3 Sensor Hub13_2 Sensor Hub13_1 Sensor Hub13_0 Table 348.
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LSM6DSO SENSOR_HUB_16 (11h) 15.16 SENSOR_HUB_16 (11h) Sensor hub output register (r) Sixteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 353. SENSOR_HUB_16 register Sensor Hub16_7 Sensor Hub16_6 Sensor Hub16_5 Sensor Hub16_4 Sensor Hub16_3 Sensor Hub16_2 Sensor Hub16_1 Sensor Hub16_0 Table 354. SENSOR_HUB_16 register description SensorHub16[7:0] 15.
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LSM6DSO MASTER_CONFIG (14h) 15.19 MASTER_CONFIG (14h) Master configuration register (r/w) Table 359. MASTER_CONFIG register RST_MASTER _REGS WRITE_ ONCE PASS_ START_ CONFIG THROUGH _MODE SHUB_ PU_EN MASTER_ON AUX_ SENS_ON1 AUX_ SENS_ON0 Table 360. MASTER_CONFIG register description Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. Default value: 0 RST_MASTER_REGS Slave 0 write operation is performed only at the first sensor hub cycle.
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LSM6DSO SLV0_SUBADD (16h) 15.21 SLV0_SUBADD (16h) Address of register on the first external sensor (Sensor 1) register (r/w) Table 363. SLV0_SUBADD register slave0_ reg7 slave0_ reg6 slave0_ reg5 slave0_ reg4 slave0_ reg3 slave0_ reg2 slave0_ reg1 slave0_ reg0 Table 364. SLV0_SUBADD register description slave0_reg[7:0] 15.22 Address of register on Sensor1 that has to be read/written according to the rw_0 bit value in SLV0_ADD (15h).
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LSM6DSO SLV1_SUBADD (19h) 15.24 SLV1_SUBADD (19h) Address of register on the second external sensor (Sensor 2) register (r/w) Table 369. SLV1_SUBADD register Slave1_ reg7 Slave1_ reg6 Slave1_ reg5 Slave1_ reg4 Slave1_ reg3 Slave1_ reg2 Slave1_ reg1 Slave1_ reg0 Table 370. SLV1_SUBADD register description Slave1_reg[7:0] 15.25 Address of register on Sensor 2 that has to be read/written according to the r_1 bit value in SLV1_ADD (18h).
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LSM6DSO SLV2_SUBADD (1Ch) 15.27 SLV2_SUBADD (1Ch) Address of register on the third external sensor (Sensor 3) register (r/w) Table 375. SLV2_SUBADD register Slave2_ reg7 Slave2_ reg6 Slave2_ reg5 Slave2_ reg4 Slave2_ reg3 Slave2_ reg2 Slave2_ reg1 Slave2_ reg0 Table 376. SLV2_SUBADD register description Slave2_reg[7:0] 15.28 Address of register on Sensor 3 that has to be read/written according to the r_2 bit value in SLV2_ADD (1Bh).
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LSM6DSO SLV3_SUBADD (1Fh) 15.30 SLV3_SUBADD (1Fh) Address of register on the fourth external sensor (Sensor 4) register (r/w) Table 381. SLV3_SUBADD register Slave3_ reg7 Slave3_ reg6 Slave3_ reg5 Slave3_ reg4 Slave3_ reg3 Slave3_ reg2 Slave3_ reg1 Slave3_ reg0 Table 382. SLV3_SUBADD register description Slave3_reg[7:0] 15.31 Address of register on Sensor 4 that has to be read according to the r_3 bit value in SLV3_ADD (1Eh).
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LSM6DSO STATUS_MASTER (22h) 15.33 STATUS_MASTER (22h) Sensor hub source register (r) Table 387. STATUS_MASTER register WR_ONCE_ DONE SLAVE3_ NACK SLAVE2_ NACK SLAVE1_ NACK SLAVE0_ NACK 0 0 SENS_HUB _ENDOP Table 388. STATUS_MASTER register description WR_ONCE_DONE When the bit WRITE_ONCE in MASTER_CONFIG (14h) is configured as 1, this bit is set to 1 when the write operation on slave 0 has been performed and completed.
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LSM6DSO Soldering information 16 Soldering information The LGA package is compliant with the ECOPACK®, RoHS and "Green" standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Land pattern and soldering recommendations are available at www.st.com/mems.
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LSM6DSO Package information 17 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 17.1 LGA-14L package information Figure 25. LGA-14L 2.5 x 3.0 x 0.86 mm package outline and mechanical data Pin1 indicator Pin1 indicator H 0.5 4x 1 TOP VIEW (0.
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LSM6DSO LGA-14 packing information 17.2 LGA-14 packing information Figure 26. Carrier tape information for LGA-14 package Figure 27.
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LSM6DSO LGA-14 packing information Figure 28. Reel information for carrier tape of LGA-14 package T 40mm min. Access hole at slot location B C N D A Full radius G measured at hub Tape slot in core for tape start 2.5mm min. width Table 389. Reel dimensions for carrier tape of LGA-14 package Reel dimensions (mm) DS12140 - Rev 2 A (max) 330 B (min) 1.5 C 13 ±0.25 D (min) 20.2 N (min) 60 G 12.4 +2/-0 T (max) 18.
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LSM6DSO Revision history Table 390. Document revision history Date Revision 22-Aug-2018 1 Changes Initial release Added product label indicating ST's commitment to sustainable technology Updated LA_TyOff in Table 2. Mechanical characteristics 25-Jan-2019 2 Updated footnotes in Table 4. Temperature sensor characteristics Updated Table 60.
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LSM6DSO Contents Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 Embedded low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 2.1 Tilt detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.
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LSM6DSO Contents 6.1 Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2 Accelerometer power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2.1 6.3 Gyroscope power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4 Block diagram of filters . . . . . . . . . . . . . . .
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LSM6DSO Contents 9.11 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.12 CTRL1_XL (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.13 CTRL2_G (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.14 CTRL3_C (12h) . . . . . . . . . . . . . .
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LSM6DSO Contents 9.41 TAP_CFG0 (56h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.42 TAP_CFG1 (57h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.43 TAP_CFG2 (58h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.44 TAP_THS_6D (59h) . . . . . . . . . . . . . .
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LSM6DSO Contents 11.6 EMB_FUNC_INT1 (0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.7 FSM_INT1_A (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.8 FSM_INT1_B (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.9 EMB_FUNC_INT2 (0Eh) . . . . . . . . . . . . . . . . . . .
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LSM6DSO Contents 11.36 FSM_OUTS16 (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.37 EMB_FUNC_ODR_CFG_B (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.38 STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h) . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.39 EMB_FUNC_SRC (64h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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LSM6DSO Contents 15.2 SENSOR_HUB_2 (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15.3 SENSOR_HUB_3 (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15.4 SENSOR_HUB_4 (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 15.5 SENSOR_HUB_5 (06h) . . . . . . . . . . . . . . . . . . . . . . . . .
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LSM6DSO Contents 15.32 DATAWRITE_SLV0 (21h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 15.33 STATUS_MASTER (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 16 Soldering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 17 Package information. . . . . . . . . . . . . . . . . . . . . . .
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LSM6DSO List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature sensor characteristics . . .
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LSM6DSO List of tables Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99.
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LSM6DSO List of tables Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. Table 149.
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LSM6DSO List of tables Table 160. Table 161. Table 162. Table 163. Table 164. Table 165. Table 166. Table 167. Table 168. Table 169. Table 170. Table 171. Table 172. Table 173. Table 174. Table 175. Table 176. Table 177. Table 178. Table 179. Table 180. Table 181. Table 182. Table 183. Table 184. Table 185. Table 186. Table 187. Table 188. Table 189. Table 190. Table 191. Table 192. Table 193. Table 194. Table 195. Table 196. Table 197. Table 198. Table 199. Table 200. Table 201. Table 202. Table 203.
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LSM6DSO List of tables Table 214. Table 215. Table 216. Table 217. Table 218. Table 219. Table 220. Table 221. Table 222. Table 223. Table 224. Table 225. Table 226. Table 227. Table 228. Table 229. Table 230. Table 231. Table 232. Table 233. Table 234. Table 235. Table 236. Table 237. Table 238. Table 239. Table 240. Table 241. Table 242. Table 243. Table 244. Table 245. Table 246. Table 247. Table 248. Table 249. Table 250. Table 251. Table 252. Table 253. Table 254. Table 255. Table 256. Table 257.
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LSM6DSO List of tables Table 268. Table 269. Table 270. Table 271. Table 272. Table 273. Table 274. Table 275. Table 276. Table 277. Table 278. Table 279. Table 280. Table 281. Table 282. Table 283. Table 284. Table 285. Table 286. Table 287. Table 288. Table 289. Table 290. Table 291. Table 292. Table 293. Table 294. Table 295. Table 296. Table 297. Table 298. Table 299. Table 300. Table 301. Table 302. Table 303. Table 304. Table 305. Table 306. Table 307. Table 308. Table 309. Table 310. Table 311.
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LSM6DSO List of tables Table 322. Table 323. Table 324. Table 325. Table 326. Table 327. Table 328. Table 329. Table 330. Table 331. Table 332. Table 333. Table 334. Table 335. Table 336. Table 337. Table 338. Table 339. Table 340. Table 341. Table 342. Table 343. Table 344. Table 345. Table 346. Table 347. Table 348. Table 349. Table 350. Table 351. Table 352. Table 353. Table 354. Table 355. Table 356. Table 357. Table 358. Table 359. Table 360. Table 361. Table 362. Table 363. Table 364. Table 365.
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LSM6DSO List of tables Table 376. Table 377. Table 378. Table 379. Table 380. Table 381. Table 382. Table 383. Table 384. Table 385. Table 386. Table 387. Table 388. Table 389. Table 390. SLV2_SUBADD register description . . . . . . . . . . . . SLAVE2_CONFIG register . . . . . . . . . . . . . . . . . . SLAVE2_CONFIG register description . . . . . . . . . . SLV3_ADD register . . . . . . . . . . . . . . . . . . . . . . . SLV3_ADD register description . . . . . . . . . . . . . . . SLV3_SUBADD register . . .
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LSM6DSO List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. DS12140 - Rev 2 Generic state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State machine in the LSM6DSO . . . . . . . . . . .
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LSM6DSO IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.