Datasheet

± 2g / 4g / 8g / 16g Tri-axis Digital

Accelerometer Specifications

PART NUMBER:

KX132-1211

Rev. 1.0

31-Jul-2019

tel: 607-257-1080 – fax:607-257-1146 893-12874-1907311605-0.2

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3-Wire Read and Write Registers

The registers embedded in the KX132-1211 accelerometer have 8-bit addresses. Upon power up, the Master must write to

the accelerometer’s control registers to set its operational mode. On the falling edge of nCS, a 2-byte command is written

to the appropriate control register. The first byte initiates the write to the appropriate register, and is followed by the user-

defined, data byte. The MSB (Most Significant Bit) of the register address byte will indicate “0” when writing to the register

and “1” when reading from the register. A read operation occurs over 17 clock cycles and a write operation occurs over 16

clock cycles. All commands are sent MSB first. The host must return nCS HIGH for at least one clock cycle before the

next data request. However, when data is being read from a buffer read register (BUF_READ), the nCS signal can remain

LOW until the buffer is read. Figure 8 below shows the timing diagram for carrying out an 8-bit register write operation.

NOTE** If a STOP condition is sent on the least significant bit of write data or the following master acknowledge cycle, the

last write operation is not guaranteed and it would cause unexpected register write.

SDI

SCLK

(MSB)

Figure 8: Timing Diagram for 8-Bit Register Write Operation

In order to read an 8-bit register, an 8-bit register address must be written to the accelerometer to initiate the read. The MSB

of this register address byte will indicate “0” when writing to the register and “1” when reading from the register. Upon

receiving the address, the accelerometer returns the 8-bit data stored in the addressed register. For 3-wire read

operations, one extra clock cycle between the address byte and the data output byte is required. Therefore, this

operation occurs over 17 clock cycles. All returned data is sent MSB first, and the host must return nCS HIGH for at least

one clock cycle before the next data request. Figure 9 shows the timing diagram for an 8-bit register read operation.

SDI

SCLK

HI-Z

(MSB)

Figure 9: Timing Diagram for 8-Bit Register Read Operation