Datasheet

± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
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3-Wire SPI Timing Diagram
SDI
nCS
t
3
CLK
bit 7
bit 6
bit 1
5
bit 0
bit 7
bit 1
5
bit 0
t
1
t
2
t
7
t
4
t
5
t
6
t
8
Number
Description
MIN
MAX
Units
t
1
CLK pulse width: HIGH
45
-
ns
t
2
CLK pulse width: LOW
45
-
ns
t
3
nCS LOW to first CLK rising edge
20
-
ns
t
4
nCS LOW after the final CLK falling edge to nCS HIGH
20
-
ns
t
5
SDI valid to CLK rising edge
10
-
ns
t
6
CLK rising edge to SDI input invalid
10
-
ns
t
7
CLK extra clock cycle rising edge to SDI output becomes
valid
-
-
ns
t
8
CLK falling edge to SDI output becomes valid
-
35
ns
Table 10: 3-Wire SPI Timing
Notes
1. t
7
and t
8
are only present during reads
2. Timings are for VDD of 1.8V to 3.6V with 1k pull-up resistor and maximum 20pF load
capacitor on SDI.
3. The SDO/ADDR pin is configured in a high-impedance input-state, and must be externally
tied to GND or IO_VDD