Datasheet

± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
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4-Wire Read and Write Registers
The registers embedded in the KX132-1211 accelerometer have 8-bit addresses. Upon power up, the Master must write to
the accelerometer’s control registers to set its operational mode. On the falling edge of nCS, a 2-byte command is written
to the appropriate control register. The first byte initiates the write to the appropriate register, and is followed by the user-
defined, data byte. The MSB (Most Significant Bit) of the register address byte will indicate “0” when writing to the register
and “1” when reading from the register. This operation occurs over 16 clock cycles. All commands are sent MSB first. The
host must return nCS HIGH for at least one clock cycle before the next data request. However, when data is being
read from a buffer read register (BUF_READ), the nCS signal can remain LOW until the buffer is read. Figure 5 below
shows the timing diagram for carrying out an 8-bit register write operation.
A7
A6
A5
A4
A3
A2
A1
A0
SDO
SDI
CLK
CS
D2
D1
Write Address
First 8 bits
HI-Z
HI-Z
D7
D6
D5
Second 8 bits
Last 8 bits
HI-Z
D0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5: Timing Diagram for 8-Bit Register Write Operation
In order to read an 8-bit register, an 8-bit register address must be written to the accelerometer to initiate the read. The MSB
of this register address byte will indicate “0” when writing to the register and “1” when reading from the register. Upon
receiving the address, the accelerometer returns the 8-bit data stored in the addressed register. This operation also occurs
over 16 clock cycles. All returned data is sent MSB first, and the host must return nCS HIGH for at least one clock cycle
before the next data request. Figure 6 shows the timing diagram for an 8-bit register read operation.
SDO
SDI
CLK
CS
D2
D1
D5
D6
D7
A7
A6
A5
A4
A3
A2
A1
A0
Read Address
HI-Z
First 8 bits
HI-Z
D2
D3
D4
D7
D0
D1
D6
D5
Last 8 bits
HI-Z
D0
D3
Second 8 bits
Figure 6: Timing Diagram for 8-Bit Register Read Operation