Datasheet

± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. – Ithaca, NY 14850 © 2019 Kionix – All Rights Reserved
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Data Transfer Sequences
The following information illustrates the variety of data transfers that can occur on the I
2
C bus and how the Master and Slave
interact during these transfers. Table 7 defines the I
2
C terms used during the data transfers.
Term
Definition
S
Start Condition
Sr
Repeated Start Condition
SAD
Slave Address
W
Write Bit
R
Read Bit
ACK
Acknowledge
NACK
Not Acknowledge
RA
Register Address
Data
Transmitted/Received Data
P
Stop Condition
Table 7: I
2
C Terms
Sequence 1: The Master is writing one byte to the Slave
Master
S
SAD + W
RA
DATA
P
Slave
ACK
ACK
ACK
Sequence 2: The Master is writing multiple bytes to the Slave
Master
S
SAD + W
RA
DATA
DATA
P
Slave
ACK
ACK
ACK
ACK
Sequence 3: The Master is receiving one byte of data from the Slave
Master
S
SAD + W
RA
Sr
SAD + R
NACK
P
Slave
ACK
ACK
ACK
DATA
Sequence 4: The Master is receiving multiple bytes of data from the Slave
Master
S
SAD + W
RA
Sr
SAD + R
ACK
NACK
P
Slave
ACK
ACK
ACK
DATA
DATA