Datasheet

± 2g / 4g / 8g / 16g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KX132-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. – Ithaca, NY 14850 © 2019 Kionix – All Rights Reserved
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I
2
C Operation
Transactions on the I
2
C bus begin after the Master transmits a start condition (S), which is defined as a HIGH-to-LOW
transition on the data line while the SCL line is held HIGH. The bus is considered busy after this condition. The next byte of
data transmitted after the start condition contains the Slave Address (SAD) in the seven MSBs (Most Significant Bits), and
the LSB (Least Significant Bit) tells whether the Master will be receiving data ‘1’ from the Slave or transmitting data ‘0’ to
the Slave. When a Slave Address is sent, each device on the bus compares the seven MSBs with its internally stored
address. If they match, the device considers itself addressed by the Master. The KX132-1211 Slave Address is comprised
of a user programmable part, a factory programmable part, and a fixed part, which allows for connection of multiple
accelerometers to the same I
2
C bus. The Slave Address associated with the KX132-1211 is 00111YX, where the user
programmable bit X, is determined by the assignment of ADDR (pin 1) to GND or IO_VDD. Also, the factory programmable
bit Y is set at the factory. For KX132-1211, the factory programmable bit Y is fixed to 1 (contact your Kionix sales
representative for list of available devices). Table 6 lists possible I
2
C addresses for KX132-1211. As a result, up to four
accelerometers can be implemented on a shared I
2
C bus as shown in Figure 3 (e.g. two KX132-1211 accelerometers and
two other accelerometers with factory programmable bit Y set to 0).
Y
X
Description
ADDR
pin
7-bit
Address
Address
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
I2C Wr
GND
0x1E
0x3C
0
0
1
1
1
1
0
0
I2C Rd
GND
0x1E
0x3D
0
0
1
1
1
1
0
1
I2C Wr
IO_VDD
0x1F
0x3E
0
0
1
1
1
1
1
0
I2C Rd
IO_VDD
0x1F
0x3F
0
0
1
1
1
1
1
1
Table 6: I
2
C Slave Addresses for KX132-1211
It is mandatory that receiving devices acknowledge (ACK) each transaction. Therefore, the transmitter must release the
SDA line during this ACK pulse. The receiver then pulls the data line LOW so that it remains stable LOW during the HIGH
period of the ACK clock pulse. A receiver that has been addressed, whether it is Master or Slave, is obliged to generate an
ACK after each byte of data has been received. To conclude a transaction, the Master must transmit a stop condition (P)
by transitioning the SDA line from LOW to HIGH while SCL is HIGH. The I
2
C bus is now free. Note that if the KX132-1211
is accessed through I
2
C protocol before the startup is finished a NACK signal is sent.