Data Sheet

ICM-20948
Document Number: DS-000189 Page 82 of 89
Revision: 1.3
I2C_MST_CLK
NOMINAL CLK
FREQUENCY [KHZ]
DUTY CYCLE
14 345.60 46.67%
15 345.60 46.67%
Table 23. I
2
C Master Clock Frequency
14.6 CLOCKING
The internal system clock sources include: (1) an internal relaxation oscillator, and (2) a PLL with MEMS gyroscope
oscillator as the reference clock. With the recommended clock selection setting (CLKSEL = 1), the best clock source for
optimum sensor performance and power consumption will be automatically selected based on the power mode.
Specifically, the internal relaxation oscillator will be selected when operating in accelerometer only mode, while the
PLL will be selected whenever gyroscope is on, which includes gyroscope and 6-axis modes.
As clock accuracy is critical to the preciseness of distance and angle calculations performed by DMP, it should be noted
that the internal relaxation oscillator and PLL show different performances in some aspects. The internal relaxation
oscillator is trimmed to have a consistent operating frequency at room temperature, while the PLL clock frequency
varies from part to part. The PLL frequency deviation from the nominal value in percentage is captured in register
TIMEBASE_CORRECTION_PLL, and users can factor it in during distance and angle calculations to not sacrifice
accuracy. Other than that, PLL has better frequency stability and lower frequency variation over temperature than the
internal relaxation oscillator.
14.7 LP_EN BIT-FIELD USAGE
The LP_EN bit-field (User Bank 0, PWR_MGMT_1 register, bit [5] helps to reduce the digital current. The
recommended setting for this bit-field is 1 to achieve the lowest possible current. However, when LP_EN is set to 1,
user may not be able to write to the following registers. If it is desired to write to registers in this list, it is
recommended to first set LP_EN=0, write the desired register(s), then set LP_EN=1 again:
• USER BANK 0: All registers except LP_CONFIG, PWR_MGMT_1, PWR_MGMT_2, INT_PIN_CFG, INT_ENABLE,
FIFO_COUNTH, FIFO_COUNTL, FIFO_R_W, FIFO_CFG, REG_BANK_SEL
• USER BANK 1: All registers except REG_BANK_SEL
• USER BANK 2: All registers except REG_BANK_SEL
• USER BANK 3: All registers except REG_BANK_SEL
14.8 REGISTER ACCESS USING SPI INTERFACE
Using the SPI interface, when the AP/user disables the gyroscope sensor (User Bank 0, PWR_MGMT_2 register, bits
[2:0]=111) as part of a sequence of register read or write commands, the AP/user will be required to subsequently
wait 22 µs prior to any of the following operations:
(1) Writing to any of the following registers:
• USER BANK 0: All registers except LP_CONFIG, PWR_MGMT_1, PWR_MGMT_2, INT_PIN_CFG, INT_ENABLE,
FIFO_COUNTH, FIFO_COUNTL, FIFO_R_W, FIFO_CFG, REG_BANK_SEL
• USER BANK 1: All registers except REG_BANK_SEL
• USER BANK 2: All registers except REG_BANK_SEL
• USER BANK 3: All registers except REG_BANK_SEL
(2) Reading data from FIFO
(3) Reading from memory