Data Sheet

ICM-20948
Document Number: DS-000189 Page 63 of 89
Revision: 1.3
10.10 ODR_ALIGN_EN
Name: ODR_ALIGN_EN
Address: 9 (09h)
Type: USR2
Bank: 2
OTP: No
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
FUNCTION
7:1
-
Reserved.
0
ODR_ALIGN_EN
0: Disables ODR start-time alignment.
1: Enables ODR start-time alignment when any of the following registers is written
(with the same value or with different values): GYRO_SMPLRT_DIV,
ACCEL_SMPLRT_DIV_1, ACCEL_SMPLRT_DIV_2, I2C_MST_ODR_CONFIG.
10.11 ACCEL_SMPLRT_DIV_1
Name: ACCEL_SMPLRT_DIV_1
Address: 16 (10h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
FUNCTION
7:4
-
Reserved.
3:0
ACCEL_SMPLRT_DIV[11:8]
MSB for ACCEL sample rate div.
10.12 ACCEL_SMPLRT_DIV_2
Name: ACCEL_SMPLRT_DIV_2
Address: 17 (11h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
FUNCTION
7:0
ACCEL_SMPLRT_DIV[7:0]
LSB for ACCEL sample rate div.
ODR is computed as follows:
1.125 kHz/(1+ACCEL_SMPLRT_DIV[11:0])
10.13 ACCEL_INTEL_CTRL
Name: ACCEL_INTEL_CTRL
Address: 18 (12h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT NAME FUNCTION
7:2
-
Reserved.
1
ACCEL_INTEL_EN
Enable the WOM logic.
0
ACCEL_INTEL_MODE_INT
Selects WOM algorithm.
1 = Compare the current sample with the previous sample.
0 = Initial sample is stored, all future samples are compared to the initial sample.