Data Sheet

ICM-20948
Document Number: DS-000189 Page 5 of 89
Revision: 1.3
9.13 TIMEBASE_CORRECTION_PLL ........................................................................................................................... 57
9.14 REG_BANK_SEL ................................................................................................................................................. 58
10 USR BANK 2 REGISTER MAP ........................................................................................................................... 59
10.1 GYRO_SMPLRT_DIV .......................................................................................................................................... 59
10.2 GYRO_CONFIG_1 .............................................................................................................................................. 59
10.3 GYRO_CONFIG_2 .............................................................................................................................................. 60
10.4 XG_OFFS_USRH ................................................................................................................................................ 61
10.5 XG_OFFS_USRL ................................................................................................................................................. 62
10.6 YG_OFFS_USRH ................................................................................................................................................ 62
10.7 YG_OFFS_USRL ................................................................................................................................................. 62
10.8 ZG_OFFS_USRH................................................................................................................................................. 62
10.9 ZG_OFFS_USRL ................................................................................................................................................. 62
10.10 ODR_ALIGN_EN ............................................................................................................................................ 63
10.11 ACCEL_SMPLRT_DIV_1 ................................................................................................................................. 63
10.12 ACCEL_SMPLRT_DIV_2 ................................................................................................................................. 63
10.13 ACCEL_INTEL_CTRL ....................................................................................................................................... 63
10.14 ACCEL_WOM_THR ........................................................................................................................................ 64
10.15 ACCEL_CONFIG ............................................................................................................................................. 64
10.16 ACCEL_CONFIG_2 ......................................................................................................................................... 65
10.17 FSYNC_CONFIG ............................................................................................................................................. 66
10.18 TEMP_CONFIG .............................................................................................................................................. 67
10.19 MOD_CTRL_USR ........................................................................................................................................... 67
10.20 REG_BANK_SEL ............................................................................................................................................. 67
11 USR BANK 3 REGISTER MAP ........................................................................................................................... 68
11.1 I2C_MST_ODR_CONFIG .................................................................................................................................... 68
11.2 I2C_MST_CTRL .................................................................................................................................................. 68
11.3 I2C_MST_DELAY_CTRL ...................................................................................................................................... 69
11.4 I2C_SLV0_ADDR ................................................................................................................................................ 69
11.5 I2C_SLV0_REG................................................................................................................................................... 69
11.6 I2C_SLV0_CTRL ................................................................................................................................................. 70
11.7 I2C_SLV0_DO .................................................................................................................................................... 70
11.8 I2C_SLV1_ADDR ................................................................................................................................................ 70
11.9 I2C_SLV1_REG................................................................................................................................................... 71
11.10 I2C_SLV1_CTRL ............................................................................................................................................. 71
11.11 I2C_SLV1_DO ................................................................................................................................................ 72
11.12 I2C_SLV2_ADDR ............................................................................................................................................ 72
11.13 I2C_SLV2_REG............................................................................................................................................... 72
11.14 I2C_SLV2_CTRL ............................................................................................................................................. 73
11.15 I2C_SLV2_DO ................................................................................................................................................ 73
11.16 I2C_SLV3_ADDR ............................................................................................................................................ 73
11.17 I2C_SLV3_REG............................................................................................................................................... 74
11.18 I2C_SLV3_CTRL ............................................................................................................................................. 74
11.19 I2C_SLV3_DO ................................................................................................................................................ 74
11.20 I2C_SLV4_ADDR ............................................................................................................................................ 75
11.21 I2C_SLV4_REG............................................................................................................................................... 75
11.22 I2C_SLV4_CTRL ............................................................................................................................................. 75
11.23 I2C_SLV4_DO ................................................................................................................................................ 75
11.24 I2C_SLV4_DI .................................................................................................................................................. 76
11.25 REG_BANK_SEL ............................................................................................................................................. 76