Data Sheet

ICM-20948
Document Number: DS-000189 Page 40 of 89
Revision: 1.3
8.10 INT_ENABLE_3
Name: INT_ENABLE_3
Address: 19 (13h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
FUNCTION
7:5
-
Reserved.
4:0
FIFO_WM_EN[4:0]
1 – Enable interrupt for FIFO watermark to propagate to interrupt pin 1.
0 – Function is disabled.
8.11 I2C_MST_STATUS
Name: I2C_MST_STATUS
Address: 23 (17h)
Type: USR0
Bank: 0
Serial IF: R/C
Reset Value: 0x00
BIT
NAME
FUNCTION
7
PASS_THROUGH
Status of FSYNC interrupt – used as a way to pass an external interrupt through this
chip to the host. If enabled in the INT_PIN_CFG register by asserting bit
FSYNC_INT_MODE_EN, this will cause an interrupt. A read of this register clears all
status bits in this register.
6
I2C_SLV4_DONE
Asserted when I
2
C slave 4’s transfer is complete, will cause an interrupt if bit
I2C_MST_INT_EN in the INT_ENABLE register is asserted, and if the
SLV4_DONE_INT_EN bit is asserted in the I2C_SLV4_CTRL register.
5
I2C_LOST_ARB
Asserted when I
2
C slave loses arbitration of the I
2
C bus, will cause an interrupt if bit
I2C_MST_INT_EN in the INT_ENABLE register is asserted.
4
I2C_SLV4_NACK
Asserted when slave 4 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
3
I2C_SLV3_NACK
Asserted when slave 3 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
2
I2C_SLV2_NACK
Asserted when slave 2 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
1
I2C_SLV1_NACK
Asserted when slave 1 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
0
I2C_SLV0_NACK
Asserted when slave 0 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
8.12 INT_STATUS
Name: INT_STATUS
Address: 25 (19h)
Type: USR0
Bank: 0
Serial IF: R/C
Reset Value: 0x00
BIT
NAME
FUNCTION
7:4
-
Reserved.
3
WOM_INT
1 – Wake on motion interrupt occurred.
2
PLL_RDY_INT
1 – Indicates that the PLL has been enabled and is ready (delay of 4 ms ensures lock).
1
DMP_INT1
1 – Indicates the DMP has generated INT1 interrupt.
0
I2C_MST_INT
1 – Indicates I
2
C master has generated an interrupt.