Data Sheet

ICM-20948
Document Number: DS-000189 Page 38 of 89
Revision: 1.3
8.5 PWR_MGMT_2
Name: PWR_MGMT_2
Address: 7 (07h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
FUNCTION
7:6
-
Reserved.
5:3
DISABLE_ACCEL
Only the following values are applicable:
111 – Accelerometer (all axes) disabled.
000 – Accelerometer (all axes) on.
2:0
DISABLE_GYRO
Only the following values are applicable:
111 – Gyroscope (all axes) disabled.
000 – Gyroscope (all axes) on.
8.6 INT_PIN_CFG
Name: INT_PIN_CFG
Address: 15 (0Fh)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT NAME FUNCTION
7
INT1_ACTL
1 – The logic level for INT1 pin is active low.
0 – The logic level for INT1 pin is active high.
6
INT1_OPEN
1 – INT1 pin is configured as open drain.
0 – INT1 pin is configured as push-pull.
5
INT1_LATCH__EN
1 – INT1 pin level held until interrupt status is cleared.
0 – INT1 pin indicates interrupt pulse is width 50 µs.
4
INT_ANYRD_2CLEAR
1 – Interrupt status in INT_STATUS is cleared (set to 0) if any read operation is
performed.
0 – Interrupt status in INT_STATUS is cleared (set to 0) only by reading INT_STATUS
register.
This bit only affects the interrupt status bits that are contained in the register
INT_STATUS, and the corresponding hardware interrupt.
This bit does not affect the interrupt status bits that are contained in registers
INT_STATUS_1, INT_STATUS_2, INT_STATUS_3, and the corresponding hardware
interrupt.
3
ACTL_FSYNC
1 – The logic level for the FSYNC pin as an interrupt to the ICM-20948 is active low.
0 – The logic level for the FSYNC pin as an interrupt to the ICM-20948 is active high.
2
FSYNC_INT_MODE_EN
1 – This enables the FSYNC pin to be used as an interrupt. A transition to the active
level described by the ACTL_FSYNC bit will cause an interrupt. The status of the
interrupt is read in the I
2
C Master Status register PASS_THROUGH bit.
0 – This disables the FSYNC pin from causing an interrupt.
1
BYPASS_EN
When asserted, the I2C_MASTER interface pins (ES_CL and ES_DA) will go into
‘bypass mode’ when the I
2
C master interface is disabled.
0
-
Reserved.