Data Sheet

ICM-20948
Document Number: DS-000189 Page 36 of 89
Revision: 1.3
8 USER BANK 0 REGISTER DESCRIPTIONS
This section describes the function and contents of the User Bank 0 Register Map within the ICM-20948.
NOTE: The device will come up in sleep mode upon power-up.
8.1 WHO_AM_I
Name: WHO_AM_I
Address: 0 (00h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0xEA
BIT NAME FUNCTION
7:0
WHO_AM_I[7:0]
Register to indicate to user which device is being accessed.
The value for ICM-20948 is 0xEA.
8.2 USER_CTRL
Name: USER_CTRL
Address: 3 (03h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
FUNCTION
7
DMP_EN
1 – Enables DMP features.
0 – DMP features are disabled after the current processing round has completed.
6
FIFO_EN
1 – Enable FIFO operation mode.
0 – Disable FIFO access from serial interface.
To disable FIFO writes by DMA, use FIFO_EN register. To disable possible FIFO writes
from DMP, disable the DMP.
5
I2C_MST_EN
1 – Enable the I
2
C Master I/F module; pins ES_DA and ES_SCL are isolated from pins
SDA/SDI and SCL/ SCLK.
0 – Disable I
2
C Master I/F module; pins ES_DA and ES_SCL are logically driven by pins
SDA/SDI and SCL/ SCLK.
4
I2C_IF_DIS
1 – Reset I
2
C Slave module and put the serial interface in SPI mode only.
3
DMP_RST
1 – Reset DMP module. Reset is asynchronous. This bit auto clears after one clock
cycle of the internal 20 MHz clock.
2
SRAM_RST
1 – Reset SRAM module. Reset is asynchronous. This bit auto clears after one clock
cycle of the internal 20 MHz clock.
1
I2C_MST_RST
1 – Reset I
2
C Master module. Reset is asynchronous. This bit auto clears after one
clock cycle of the internal 20 MHz clock.
NOTE: This bit should only be set when the I
2
C master has hung. If this bit is set during an active
I
2
C master transaction, the I
2
C slave will hang, which will require the host to reset the slave.
0
-
Reserved.