Data Sheet

ICM-20948
Document Number: DS-000189 Page 17 of 89
Revision: 1.3
3.6 SPI TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, T
A
=25°C, unless otherwise noted.
PARAMETERS CONDITIONS MIN TYPICAL MAX UNITS NOTES
SPI TIMING
f
SCLK
, SCLK Clock Frequency 7 MHz
t
LOW
, SCLK Low Period 64 ns
t
HIGH
, SCLK High Period 64 ns
t
SU.CS
, CS Setup Time 8 ns
t
HD.CS
, CS Hold Time 500 ns
t
SU.SDI
, SDI Setup Time
5
ns
t
HD.SDI
, SDI Hold Time 7 ns
t
VD.SDO
, SDO Valid Time C
load
= 20 pF 59 ns
t
HD.SDO
, SDO Hold Time C
load
= 20 pF 6 ns
t
DIS.SDO
, SDO Output Disable Time
50
ns
Table 8. SPI Timing Characteristics (7 MHz)
NOTES:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
t HIGH
70%
30%
1/f
CLK
t HD;CS
CS
SCLK
SDI
SDO
MSB OUT
MSB IN
LSB IN
LSB OUT
t
DIS;SDO
70%
30%
t SU;CS
t SU;SDI t HD;SDI
70%
30%
t HD;SDO
70%
30%
t VD;SDO
t LOW
Figure 2. SPI Bus Timing Diagram