Data Sheet

ICM-20948
Document Number: DS-000189 Page 16 of 89
Revision: 1.3
3.5 I
2
C TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, T
A
=25°C, unless otherwise noted.
PARAMETERS CONDITIONS MIN TYPICAL MAX UNITS NOTES
I
2
C TIMING I
2
C FAST-MODE
f
SCL
, SCL Clock Frequency
400
kHz
1, 2
t
HD.STA
, (Repeated) START Condition Hold
Time
0.6
µs
1, 2
t
LOW
, SCL Low Period
1.3
µs
1, 2
t
HIGH
, SCL High Period
0.6
µs
1, 2
t
SU.STA
, Repeated START Condition Setup
Time
0.6
µs
1, 2
t
HD.DAT
, SDA Data Hold Time
0
µs
1, 2
t
SU.DAT
, SDA Data Setup Time
100
ns
1, 2
t
r
, SDA and SCL Rise Time
C
b
bus cap. from 10 to 400 pF
20+0.1C
b
300
ns
1, 2
t
f
, SDA and SCL Fall Time
C
b
bus cap. from 10 to 400 pF
20+0.1C
b
300
ns
1, 2
t
SU.STO
, STOP Condition Setup Time
0.6
µs
1, 2
t
BUF
, Bus Free Time Between STOP and
START Condition
1.3
µs
1, 2
C
b
, Capacitive Load for each Bus Line
< 400
pF
1, 2
t
VD.DAT
, Data Valid Time
0.9
µs
1, 2
t
VD.ACK
, Data Valid Acknowledge Time
0.9
µs
1, 2
Table 7. I
2
C Timing Characteristics
NOTES:
1. Timing Characteristics apply to both Primary and Auxiliary I
2
C Bus.
2. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
SDA
SCL
SDA
SCL
70%
30%
t f
S
70%
30%
t r
tSU.DAT
t
r
tHD.DAT
70%
30%
t
HD.STA
1/f
SCL
1
st
clock cycle
70%
30%
tLOW
tHIGH
t
VD.DAT
9
th
clock cycle
continued below at A
A
Sr
P
S
70%
30%
tSU.STA
tHD.STA
tVD.ACK
tSU.STO
t
BUF
70%
30%
9
th
clock cycle
t f
Figure 1. I
2
C Bus Timing Diagram