Data Sheet

VEML6075
www.vishay.com
Vishay Semiconductors
Rev. 1.2, 23-Nov-16
4
Document Number: 84304
For technical questions, contact: [e-mail]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PARAMETER TIMING INFORMATION
Fig. 2 - I
2
C Bus Timing for Sending Word Command Format
Fig. 3 - I
2
C Timing for Receive Word Command Format
ACK by
VEML6075
ACK by
VEML6075
ACK by
VEML6075
ACK by
VEML6075
I
2
C bus
clock
(SCLK)
I
2
C bus
data
(SDAT)
I
2
C bus
clock
(SCLK)
I
2
C bus
data
(SDAT)
I
2
C bus slave address byte Command code
Start by
master
Stop by
master
Data byte low Data byte high
SA7 SA1SA2SA3SA4SA5SA6 SA7 SA1SA2SA3SA4SA5SA6 SA0
SA7 SA1SA2SA3SA4SA5SA6 SA0
SA7
SA1SA2SA3SA4SA5SA6
SA0
W
ACK by
VEML6075
ACK by
VEML6075
ACK by
VEML6075
I
2
C bus
clock
(SCLK)
I
2
C bus
data
(SDAT)
I
2
C bus slave address byte Command code
Start by
master
SA7 SA1SA2SA3SA4SA5SA6 SA7 SA1SA2SA3SA4SA5SA6
SA0
W
I
2
C bus
clock
(SCLK)
I
2
C bus
data
(SDAT)
Data byte low
Data byte high
ACK by
master
Start by
master
I
2
C bus slave address byte
I
2
C bus
clock
(SCLK)
I
2
C bus
data
(SDAT)
ACK by
master
Stop by
master
SA7 SA1SA2SA3SA4SA5SA6
SA7 SA1SA2SA3SA4SA5SA6 SA0
R
SA7 SA1SA2SA3SA4SA5SA6 SA0