User Manual

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ID Register (0x92)
The read-only ID Register provides the device identication.
Field Bits Description
ID 7:0 Part number identication.
0xAB = APDS-9960
Status Register (0x93)
The read-only Status Register provides the status of the device. The register is set to 0x04 at power-up.
Field Bits Description
CPSAT 7 Clear Photodiode Saturation. When asserted, the analog sensor was at the upper end of its
dynamic range. The bit can be de-asserted by sending a Clear channel interrupt command
(0xE6 CICLEAR) or by disabling the ADC (AEN=0). This bit triggers an interrupt if CPSIEN is set.
PGSAT 6 Indicates that an analog saturation event occurred during a previous proximity or gesture
cycle. Once set, this bit remains set until cleared by clear proximity interrupt special function
command (0xE5 PICLEAR) or by disabling Prox (PEN=0). This bit triggers an interrupt if PSIEN
is set.
PINT 5 Proximity Interrupt. This bit triggers an interrupt if PIEN in ENABLE is set.
AINT 4 ALS Interrupt. This bit triggers an interrupt if AIEN in ENABLE is set.
RESERVED 3 Do not care.
GINT 2 Gesture Interrupt. GINT is asserted when GFVLV becomes greater than GFIFOTH or if GVALID
has become asserted when GMODE transitioned to zero. The bit is reset when FIFO is
completely emptied (read).
PVALID 1 Proximity Valid. Indicates that a proximity cycle has completed since PEN was asserted or since
PDATA was last read. A read of PDATA automatically clears PVALID.
AVALID 0 ALS Valid. Indicates that an ALS cycle has completed since AEN was asserted or since a read
from any of the ALS/Color data registers.
RGBC Data Register (0x94 – 0x9B)
Red, green, blue, and clear data is stored as 16-bit values. The read sequence must read byte pairs (low followed by high)
starting on an even address boundary (0x94, 0x96, 0x98, or 0x9A) inside the RGBC Data Register block. When the lower
byte register is read, the upper eight bits are stored into a shadow register, which is read by a subsequent read to the
upper byte. The upper register will read the correct value even if additional ADC integration cycles end between the
reading of the lower and upper registers.
Field Address Bits Description
CDATAL 0x94 7:0 Low Byte of clear channel data.
CDATAH 0x95 7:0 High Byte of clear channel data.
RDATAL 0x96 7:0 Low Byte of red channel data.
RDATAH 0x97 7:0 High Byte of red channel data.
GDATAL 0x98 7:0 Low Byte of green channel data.
GDATAH 0x99 7:0 High Byte of green channel data.
BDATAL 0x9A 7:0 Low Byte of blue channel data.
BDATAH 0x9B 7:0 High Byte of blue channel data.
Note: When reading register contents, a read of the lower byte data automatically latches the corresponding higher byte data (16 bit latch). This
feature guarantees that the high byte value has not been updated by the ADC between I2C reads. In addition, reading CDATAL register not only latches
CDATAH but also latches all eight RGBC register simultaneously (64 bit latch).