User Manual
21
ALS Interrupt Threshold Register (0x84 – 0x87)
ALS level detection uses data generated by the Clear Channel. The ALS Interrupt Threshold registers provide 16-bit
values to be used as the high and low thresholds for comparison to the 16-bit CDATA values. If AIEN is enabled and
CDATA is greater than AILTH/AIHTH or less than AILTL/AIHTL for the number of consecutive samples specied in APERS
an interrupt is asserted on the interrupt pin.
Field Address Bits Description
AILTL 0x84 7:0 This register provides the low byte of the low interrupt threshold.
AILTH 0x85 7:0 This register provides the high byte of the low interrupt threshold.
AIHTL 0x86 7:0 This register provides the low byte of the high interrupt threshold.
AIHTH 0x87 7:0 This register provides the high byte of the high interrupt threshold.
Proximity Interrupt Threshold Register (0x89/0x8B)
The Proximity Interrupt Threshold Registers set the high and low trigger points for the comparison function which gen-
erates an interrupt. If PDATA, the value generated by proximity channel, crosses below the lower threshold specied, or
above the higher threshold, an interrupt may be signaled to the host processor. Interrupt generation is subject to the
value set in persistence (PERS).
Field Address Bits Description
PILT 0x89 7:0 This register provides the low interrupt threshold.
PIHT 0x8B 7:0 This register provides the high interrupt threshold.
Wait Time Register (0x83)
The WTIME controls the amount of time in a low power mode between Proximity and/or ALS cycles. It is set 2.78ms
increments unless the WLONG bit is asserted in which case the wait times are 12× longer. WTIME is programmed as a 2’s
complement number. Upon power up, the wait time register is set to 0xFF.
Field Bits Description
WTIME 7:0
FIELD VALUE WAIT TIME TIME (WLONG = 0) TIME (WLONG = 1)
0 256 712 ms 8.54 s
= 256 – TIME / 2.78 ms … …
171 85 236 ms 2.84 s
255 1 2.78 ms 0.03 s
Notes:
1. The wait time register should be congured before AEN and/or PEN is asserted.
2. During any Proximity and/or ALS cycle, the wait state, depicted in the functional block diagram, is entered. For example, Prox only, Prox and ALS,
or ALS only cycles always enter the WAIT state and are separated by the time dened by WTIME.