Datasheet
Table Of Contents
- General Description
- Key Features
- Applications
- System Diagrams
- Contents
- Figures
- Tables
- Legal
- Product Family
- 1 Terms and Definitions
- 2 Block Diagram
- 3 Pinout
- 4 Characteristics
- 5 Functional Description
- 5.1 Features Description
- Driving LRA and ERM Actuators
- Automatic LRA Resonant Frequency Tracking
- Wideband LRA Support
- I2C and PWM Input Streaming
- Low Latency I2C/GPI Wake-Up from IDLE State
- Three GPI Sequence Triggers for up to Six Independent Haptic Responses
- On-Board Waveform Memory with Amplitude, Time, and Frequency Control
- Active Acceleration and Rapid Stop for High-Fidelity Haptic Feedback
- Continuous Actuator Diagnostics and Fault Handling
- No Software Requirements with Embedded Operation
- Differential Output Drive
- Current Driven System
- Configurable EMI Suppression
- Automatic Short Circuit Protection
- Ultra-Low Power Consumption with State Retention
- Ultra-Low Latency in STANDBY State
- Supply Monitoring, Reporting, and Automatic Output Limiting
- Open- and Closed-Loop Modes
- Open-Loop Sine/Custom Wave Drive Support
- Small Solution Footprint
- Additional Features
- 5.2 Functional Modes
- 5.3 Resonant Frequency Tracking
- 5.4 Active Acceleration and Rapid Stop
- 5.5 Wideband Frequency Control
- 5.6 Device Configuration and Playback
- 5.7 Advanced Operation
- 5.7.1 Frequency Tracking
- 5.7.2 Rapid Stop
- 5.7.3 Initial Impedance Update
- 5.7.4 Amplitude PID
- 5.7.5 Wideband Operation
- 5.7.6 Custom Waveform Operation
- 5.7.7 Embedded Operation
- 5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode
- 5.7.9 Loop Filter Configuration
- 5.7.10 UVLO Threshold
- 5.7.11 Edge Rate Control
- 5.7.12 Double Output Current Range
- 5.7.13 Supply Monitoring, Reporting, and Automatic Output Limiting
- 5.7.14 BEMF Fault Limit
- 5.7.15 Increasing Impedance Detection Accuracy
- 5.7.16 Frequency Pause during Rapid Stop
- 5.7.17 Frequency Pause during Rapid Stop
- 5.7.18 Coin ERM Operation
- 5.8 Waveform Memory
- 5.9 General Data Format
- 5.10 I2C Control Interface
- 5.1 Features Description
- 6 Register Overview
- 7 Package Information
- 8 Ordering Information
- 9 Application Information
- 10 Layout Guidelines
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Datasheet
Revision 3.0
30-Jul-2019
CFR0011-120-00
75 of 76
© 2019 Dialog Semiconductor
10 Layout Guidelines
For optimal layout, place the 100 nF capacitor as close to VDD and GND_1 pins as possible. It is
also advisable to use solid a ground plane under the device.
The QFN can be routed out on a single layer. It is recommended to connect GND_1 and GND_2 to a
local ground plane on the top layer with a low-impedance via connection to the main ground plane,
see Figure 43.
nIRQ
VIAVIA VIAVIA
VIAVIA
VIA TO
VDD
LAYER
VIA TO GND LAYER
SOLID GND
CONNECTION
ON TOP LAYER
VIA TO
VDDIO
LAYER
100 nF Capacitor
0201 (0603)
SCL SDA
GPI_1
GPI_2 VDDIO
GPI_0/
PWM
OUTN GND_2
VDD OUTP GND_1
Figure 42: WLCSP Example PCB Layout
VIAVIA
VIAVIA
VIAS TO
GND LAYER
SOLID GND
CONNECTION
ON TOP LAYER
VIA TO
VDDIO
LAYER
100 nF Capacitor
0603 (1608)
VIA
VIA
nIRQ SCL SDA
VDDIO
OUTN
GND_1
GND_2
OUTPVDD
GPI_2
GPI_1
GPI_0/PWM
Figure 43: QFN Example PCB Layout