Datasheet
Table Of Contents
- General Description
- Key Features
- Applications
- System Diagrams
- Contents
- Figures
- Tables
- Legal
- Product Family
- 1 Terms and Definitions
- 2 Block Diagram
- 3 Pinout
- 4 Characteristics
- 5 Functional Description
- 5.1 Features Description
- Driving LRA and ERM Actuators
- Automatic LRA Resonant Frequency Tracking
- Wideband LRA Support
- I2C and PWM Input Streaming
- Low Latency I2C/GPI Wake-Up from IDLE State
- Three GPI Sequence Triggers for up to Six Independent Haptic Responses
- On-Board Waveform Memory with Amplitude, Time, and Frequency Control
- Active Acceleration and Rapid Stop for High-Fidelity Haptic Feedback
- Continuous Actuator Diagnostics and Fault Handling
- No Software Requirements with Embedded Operation
- Differential Output Drive
- Current Driven System
- Configurable EMI Suppression
- Automatic Short Circuit Protection
- Ultra-Low Power Consumption with State Retention
- Ultra-Low Latency in STANDBY State
- Supply Monitoring, Reporting, and Automatic Output Limiting
- Open- and Closed-Loop Modes
- Open-Loop Sine/Custom Wave Drive Support
- Small Solution Footprint
- Additional Features
- 5.2 Functional Modes
- 5.3 Resonant Frequency Tracking
- 5.4 Active Acceleration and Rapid Stop
- 5.5 Wideband Frequency Control
- 5.6 Device Configuration and Playback
- 5.7 Advanced Operation
- 5.7.1 Frequency Tracking
- 5.7.2 Rapid Stop
- 5.7.3 Initial Impedance Update
- 5.7.4 Amplitude PID
- 5.7.5 Wideband Operation
- 5.7.6 Custom Waveform Operation
- 5.7.7 Embedded Operation
- 5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode
- 5.7.9 Loop Filter Configuration
- 5.7.10 UVLO Threshold
- 5.7.11 Edge Rate Control
- 5.7.12 Double Output Current Range
- 5.7.13 Supply Monitoring, Reporting, and Automatic Output Limiting
- 5.7.14 BEMF Fault Limit
- 5.7.15 Increasing Impedance Detection Accuracy
- 5.7.16 Frequency Pause during Rapid Stop
- 5.7.17 Frequency Pause during Rapid Stop
- 5.7.18 Coin ERM Operation
- 5.8 Waveform Memory
- 5.9 General Data Format
- 5.10 I2C Control Interface
- 5.1 Features Description
- 6 Register Overview
- 7 Package Information
- 8 Ordering Information
- 9 Application Information
- 10 Layout Guidelines
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Datasheet
Revision 3.0
30-Jul-2019
CFR0011-120-00
70 of 76
© 2019 Dialog Semiconductor
Table 73: IRQ_STATUS2 (0x0082)
Bit
Mode
Symbol
Description
Reset
[7]
RO
STA_ADC_SAT
Status of ADC saturation fault: ADC_SAT_FAULT
0x0
Table 74: IRQ_MASK2 (0x0083)
Bit
Mode
Symbol
Description
Reset
[7]
RW
ADC_SAT_M
Masking for ADC saturation fault: ADC_SAT_FAULT
0x0
Register SNP_MEM_xx
Table 75 shows the first, intermediary, and last snippet memory registers.
● The snippet register addresses increment by 1 for each snippet.
● The Bit ([7:0]), Mode (RW), and Reset (0x0) are identical for each snippet register.
● For further details on the Waveform Memory, see Section 5.8.
Table 75: SNP_MEM_xx (0x0084 to 0x00E7)
Bit
Mode
Symbol
Description
Reset
[7:0]
RW
SNP_MEM_00
Snippet memory byte 0
0x0
[7:0]
RW
SNP_MEM_xx
Snippet memory byte x
0x0
[7:0]
RW
SNP_MEM_99
Snippet memory byte 99
0x0