Datasheet
Table Of Contents
- General Description
- Key Features
- Applications
- System Diagrams
- Contents
- Figures
- Tables
- Legal
- Product Family
- 1 Terms and Definitions
- 2 Block Diagram
- 3 Pinout
- 4 Characteristics
- 5 Functional Description
- 5.1 Features Description
- Driving LRA and ERM Actuators
- Automatic LRA Resonant Frequency Tracking
- Wideband LRA Support
- I2C and PWM Input Streaming
- Low Latency I2C/GPI Wake-Up from IDLE State
- Three GPI Sequence Triggers for up to Six Independent Haptic Responses
- On-Board Waveform Memory with Amplitude, Time, and Frequency Control
- Active Acceleration and Rapid Stop for High-Fidelity Haptic Feedback
- Continuous Actuator Diagnostics and Fault Handling
- No Software Requirements with Embedded Operation
- Differential Output Drive
- Current Driven System
- Configurable EMI Suppression
- Automatic Short Circuit Protection
- Ultra-Low Power Consumption with State Retention
- Ultra-Low Latency in STANDBY State
- Supply Monitoring, Reporting, and Automatic Output Limiting
- Open- and Closed-Loop Modes
- Open-Loop Sine/Custom Wave Drive Support
- Small Solution Footprint
- Additional Features
- 5.2 Functional Modes
- 5.3 Resonant Frequency Tracking
- 5.4 Active Acceleration and Rapid Stop
- 5.5 Wideband Frequency Control
- 5.6 Device Configuration and Playback
- 5.7 Advanced Operation
- 5.7.1 Frequency Tracking
- 5.7.2 Rapid Stop
- 5.7.3 Initial Impedance Update
- 5.7.4 Amplitude PID
- 5.7.5 Wideband Operation
- 5.7.6 Custom Waveform Operation
- 5.7.7 Embedded Operation
- 5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode
- 5.7.9 Loop Filter Configuration
- 5.7.10 UVLO Threshold
- 5.7.11 Edge Rate Control
- 5.7.12 Double Output Current Range
- 5.7.13 Supply Monitoring, Reporting, and Automatic Output Limiting
- 5.7.14 BEMF Fault Limit
- 5.7.15 Increasing Impedance Detection Accuracy
- 5.7.16 Frequency Pause during Rapid Stop
- 5.7.17 Frequency Pause during Rapid Stop
- 5.7.18 Coin ERM Operation
- 5.8 Waveform Memory
- 5.9 General Data Format
- 5.10 I2C Control Interface
- 5.1 Features Description
- 6 Register Overview
- 7 Package Information
- 8 Ordering Information
- 9 Application Information
- 10 Layout Guidelines
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Datasheet
Revision 3.0
30-Jul-2019
CFR0011-120-00
69 of 76
© 2019 Dialog Semiconductor
Bit
Mode
Symbol
Description
Reset
[4:3]
RW
REF_UVLO_THRE
S
UVLO threshold, see Section 5.7.10
00 = 2.7 V
01 = 2.8 V
10 = 2.9 V
11 = 3.0 V
0x1
Table 69: TRIM4 (0x0060)
Bit
Mode
Symbol
Description
Reset
[3:2]
RW
LOOP_FILT_CAP_
TRIM
Loop capacitor trim, see Section 5.7.9
0x3
[1:0]
RW
LOOP_FILT_RES_
TRIM
Loop resistance trim, see Section 5.7.9
0x0
Table 70: TRIM6 0x(0062)
Bit
Mode
Symbol
Description
Reset
[3:2]
RW
HBRIDGE_ERC_L
S_TRIM
Low side edge rate control setting, see Section 5.7.11.
00 = 25 mV/ns
01 = 50 mV/ns
10 = 75 mV/ns
11 = 100 mV/ns
0x3
[1:0]
RW
HBRIDGE_ERC_H
S_TRIM
High side edge rate control setting, see Section 5.7.11
00 = 25 mV/ns
01 = 50 mV/ns
10 = 75 mV/ns
11 = 100 mV/ns
0x3
Table 71: D2602_TOP_CFG5 (0x006E)
Bit
Mode
Symbol
Description
Reset
[2]
RW
DELAY_BYPASS
Delay comparator bypass enable
0x0
[1]
RW
FRQ_PAUSE_ON_
POLARITY_CHANG
E
Pause the frequency update when the drive polarity changes
(during rapid stop, negative accelaration, negative DRO
value)
0x0 = Pause disabled
0x1 = Pause enabled
0x0
[0]
RW
V2I_FACTOR_OFF
SET_EN
Apply a 50 mV offset to the V2I factor calculation
0x0 = No offset applied
0x1 = 50 mV offset applied
0x1
Table 72: IRQ_EVENT_ACTUATOR_FAULT (0x0081)
Bit
Mode
Symbol
Description
Reset
[2]
RO
ADC_SAT_FAULT
ADC produced saturated result, which is not expected to
happen (write 1 to E_ACTUATOR to clear)
0x0