Datasheet
Table Of Contents
- General Description
- Key Features
- Applications
- System Diagrams
- Contents
- Figures
- Tables
- Legal
- Product Family
- 1 Terms and Definitions
- 2 Block Diagram
- 3 Pinout
- 4 Characteristics
- 5 Functional Description
- 5.1 Features Description
- Driving LRA and ERM Actuators
- Automatic LRA Resonant Frequency Tracking
- Wideband LRA Support
- I2C and PWM Input Streaming
- Low Latency I2C/GPI Wake-Up from IDLE State
- Three GPI Sequence Triggers for up to Six Independent Haptic Responses
- On-Board Waveform Memory with Amplitude, Time, and Frequency Control
- Active Acceleration and Rapid Stop for High-Fidelity Haptic Feedback
- Continuous Actuator Diagnostics and Fault Handling
- No Software Requirements with Embedded Operation
- Differential Output Drive
- Current Driven System
- Configurable EMI Suppression
- Automatic Short Circuit Protection
- Ultra-Low Power Consumption with State Retention
- Ultra-Low Latency in STANDBY State
- Supply Monitoring, Reporting, and Automatic Output Limiting
- Open- and Closed-Loop Modes
- Open-Loop Sine/Custom Wave Drive Support
- Small Solution Footprint
- Additional Features
- 5.2 Functional Modes
- 5.3 Resonant Frequency Tracking
- 5.4 Active Acceleration and Rapid Stop
- 5.5 Wideband Frequency Control
- 5.6 Device Configuration and Playback
- 5.7 Advanced Operation
- 5.7.1 Frequency Tracking
- 5.7.2 Rapid Stop
- 5.7.3 Initial Impedance Update
- 5.7.4 Amplitude PID
- 5.7.5 Wideband Operation
- 5.7.6 Custom Waveform Operation
- 5.7.7 Embedded Operation
- 5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode
- 5.7.9 Loop Filter Configuration
- 5.7.10 UVLO Threshold
- 5.7.11 Edge Rate Control
- 5.7.12 Double Output Current Range
- 5.7.13 Supply Monitoring, Reporting, and Automatic Output Limiting
- 5.7.14 BEMF Fault Limit
- 5.7.15 Increasing Impedance Detection Accuracy
- 5.7.16 Frequency Pause during Rapid Stop
- 5.7.17 Frequency Pause during Rapid Stop
- 5.7.18 Coin ERM Operation
- 5.8 Waveform Memory
- 5.9 General Data Format
- 5.10 I2C Control Interface
- 5.1 Features Description
- 6 Register Overview
- 7 Package Information
- 8 Ordering Information
- 9 Application Information
- 10 Layout Guidelines
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Datasheet
Revision 3.0
30-Jul-2019
CFR0011-120-00
63 of 76
© 2019 Dialog Semiconductor
Table 42: TOP_INT_CFG6_L (0x001D)
Bit
Mode
Symbol
Description
Reset
[7:0]
RW
FRQ_PID_Kp_L
LS-bits of the frequency tracking loop PID Kp proportional
coefficient, see Section 5.7.1 for details
0x20
Table 43: TOP_INT_CFG7_H (0x001E)
Bit
Mode
Symbol
Description
Reset
[7:0]
RW
FRQ_PID_Ki_H
MS-bits of the frequency tracking loop PID Ki integral coefficient,
see Section 5.7.1 for details
0x03
Table 44: TOP_INT_CFG7_L (0x001F)
Bit
Mode
Symbol
Description
Reset
[7:0]
RW
FRQ_PID_Ki_L
LS-bits of the frequency tracking loop PID Ki integral coefficient,
see Section 5.7.1 for details
0x20
Table 45: TOP_INT_CFG8 (0x0020)
Bit
Mode
Symbol
Description
Reset
[6:4]
RW
RAPID_STOP_
LIM
Selects the Rapid Stop threshold at which DA7280 stops driving
while braking, see Section 5.7.2
0x4
[3:0]
RW
FRQ_TRACK_
BEMF_LIM
Selects the frequency tracking threshold at which DA7280 pauses
frequency tracking, see Section 5.7.1
0x3
Table 46: TOP_CTL1 (0x0022)
Bit
Mode
Symbol
Description
Reset
[4]
RW
SEQ_START
Start/stop control of Waveform Memory sequence playback
0x0 = Stop playback and return to IDLE state
0x1 = Start playback
0x0
[3]
RW
STANDBY_E
N
Sets the state DA7280 returns to after completion of playback, see
Section 5.2.1.
0x0 = Return to IDLE state after playback
0x1 = Return to STANDBY state after playback
0x0
[2:0]
RW
OPERATION
_MODE
Haptic operation mode, see Section 5.2.
0x0 = Inactive mode
0x1 = Direct register override (DRO) mode
0x2 = Playback from PWM data source (PWM) mode
0x3 = Register triggered waveform memory (RTWM) mode
0x4 = Edge triggered waveform memory (ETWM) mode
0x0