Datasheet
Table Of Contents
- General Description
- Key Features
- Applications
- System Diagrams
- Contents
- Figures
- Tables
- Legal
- Product Family
- 1 Terms and Definitions
- 2 Block Diagram
- 3 Pinout
- 4 Characteristics
- 5 Functional Description
- 5.1 Features Description
- Driving LRA and ERM Actuators
- Automatic LRA Resonant Frequency Tracking
- Wideband LRA Support
- I2C and PWM Input Streaming
- Low Latency I2C/GPI Wake-Up from IDLE State
- Three GPI Sequence Triggers for up to Six Independent Haptic Responses
- On-Board Waveform Memory with Amplitude, Time, and Frequency Control
- Active Acceleration and Rapid Stop for High-Fidelity Haptic Feedback
- Continuous Actuator Diagnostics and Fault Handling
- No Software Requirements with Embedded Operation
- Differential Output Drive
- Current Driven System
- Configurable EMI Suppression
- Automatic Short Circuit Protection
- Ultra-Low Power Consumption with State Retention
- Ultra-Low Latency in STANDBY State
- Supply Monitoring, Reporting, and Automatic Output Limiting
- Open- and Closed-Loop Modes
- Open-Loop Sine/Custom Wave Drive Support
- Small Solution Footprint
- Additional Features
- 5.2 Functional Modes
- 5.3 Resonant Frequency Tracking
- 5.4 Active Acceleration and Rapid Stop
- 5.5 Wideband Frequency Control
- 5.6 Device Configuration and Playback
- 5.7 Advanced Operation
- 5.7.1 Frequency Tracking
- 5.7.2 Rapid Stop
- 5.7.3 Initial Impedance Update
- 5.7.4 Amplitude PID
- 5.7.5 Wideband Operation
- 5.7.6 Custom Waveform Operation
- 5.7.7 Embedded Operation
- 5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode
- 5.7.9 Loop Filter Configuration
- 5.7.10 UVLO Threshold
- 5.7.11 Edge Rate Control
- 5.7.12 Double Output Current Range
- 5.7.13 Supply Monitoring, Reporting, and Automatic Output Limiting
- 5.7.14 BEMF Fault Limit
- 5.7.15 Increasing Impedance Detection Accuracy
- 5.7.16 Frequency Pause during Rapid Stop
- 5.7.17 Frequency Pause during Rapid Stop
- 5.7.18 Coin ERM Operation
- 5.8 Waveform Memory
- 5.9 General Data Format
- 5.10 I2C Control Interface
- 5.1 Features Description
- 6 Register Overview
- 7 Package Information
- 8 Ordering Information
- 9 Application Information
- 10 Layout Guidelines
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Datasheet
Revision 3.0
30-Jul-2019
CFR0011-120-00
55 of 76
© 2019 Dialog Semiconductor
Addr
Register
7
6
5
4
3
2
1
0
Reset
0x1F
TOP_INT_CF
G7_L
FRQ_PID_Ki_L<7:0>
0x20
0x20
TOP_INT_CF
G8
Reserved
0
RAPID_STOP_LIM<2:0>
FRQ_TRACK_BEMF_LIM<3:0>
0x43
0x22
TOP_CTL1
Reserved
Reserved
Reserved
SEQ_STA
RT
STANDBY
_EN
OPERATION_MODE<2:0>
0x00
0x23
TOP_CTL2
OVERRIDE_VAL<7:0>
0x00
0x24
SEQ_CTL1
Reserved
Reserved
Reserved
Reserved
Reserved
FREQ_W
AVEFOR
M_TIME
BASE
WAVEGE
N_MODE
SEQ_C
ONTINU
E
0x08
0x25
SWG_C1
CUSTOM_WAVE_GEN_COEFF1<7:0>
0x61
0x26
SWG_C2
CUSTOM_WAVE_GEN_COEFF2<7:0>
0xB4
0x27
SWG_C3
CUSTOM_WAVE_GEN_COEFF3<7:0>
0xEC
0x28
SEQ_CTL2
PS_SEQ_LOOP<3:0>
PS_SEQ_ID<3:0>
0x00
0x29
GPI_0_CTL
Reserved
GPI0_SEQUENCE_ID<3:0>
GPI0_M
ODE
GPI0_POLARITY<1:0
>
0x00
0x2A
GPI_1_CTL
Reserved
GPI1_SEQUENCE_ID<3:0>
GPI1_M
ODE
GPI1_POLARITY<1:0
>
0x08
0x2B
GPI_2_CTL
Reserved
GPI2_SEQUENCE_ID<3:0>
GPI2_M
ODE
GPI2_POLARITY<1:0
>
0x10
0x2C
MEM_CTL1
WAV_MEM_BASE_ADDR <7:0>
0x84
0x2D
MEM_CTL2
WAV_ME
M_LOCK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserve
d
0x80
0x2E
ADC_DATA_
H1
ADC_VDD_H<7:0>
0xFF
0x2F
ADC_DATA_
L1
Reserved
ADC_VDD_L<6:0>
0x7F
0x43
POLARITY
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
POLARI
TY
0x00
0x44
LRA_AVR_H
LRA_PER_AVERAGE_H<7:0>
0x00
0x45
LRA_AVR_L
Reserved
LRA_PER_AVERAGE_L<6:0>
0x00
0x46
FRQ_LRA_P
ER_ACT_H
LRA_PER_ACTUAL_H<7:0>
0x21
0x47
FRQ_LRA_P
ER_ACT_L
Reserved
LRA_PER_ACTUAL_L<6:0>
0x4F
0x48
FRQ_PHASE
_H
DELAY_H<7:0>
0x25
0x49
FRQ_PHASE
_L
DELAY_
FREEZE
Reserved
Reserved
Reserved
Reserved
DELAY_SHIFT_L<2:0>
0x05
0x4C
FRQ_CTL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FREQ_T
RACKIN
G_AUTO
_ADJ
FREQ_T
RACKIN
G_FOR
CE_ON
0x02
0x5F
TRIM3
Reserved
LOOP_ID
AC_DOU
BLE_RA
NGE
LOOP_FI
LT_LOW
_BW
REF_UVLO_THRES
Reserved
Reserved
Reserve
d
0x0E
0x60
TRIM4
Reserved
Reserved
Reserved
Reserved
LOOP_FILT_CAP_TRIM
<1:0>
LOOP_FILT_RES_TRI
M<1:0>
0x9C
0x62
TRIM6
Reserved
Reserved
Reserved
Reserved
HBRIDGE_ERC_LS_TRI
M<1:0>
HBRIDGE_ERC_HS_
TRIM<1:0>
0x5F
0x6E
TOP_CFG5
Reserved
Reserved
Reserved
Reserved
Reserved
DELAY_
BYPASS
FRQ_PA
USE_ON
_POLARI
TY_CHA
NGE
V2I_FAC
TOR_OF
FSET_E
N
0x01