Datasheet
Table Of Contents
- General Description
- Key Features
- Applications
- System Diagrams
- Contents
- Figures
- Tables
- Legal
- Product Family
- 1 Terms and Definitions
- 2 Block Diagram
- 3 Pinout
- 4 Characteristics
- 5 Functional Description
- 5.1 Features Description
- Driving LRA and ERM Actuators
- Automatic LRA Resonant Frequency Tracking
- Wideband LRA Support
- I2C and PWM Input Streaming
- Low Latency I2C/GPI Wake-Up from IDLE State
- Three GPI Sequence Triggers for up to Six Independent Haptic Responses
- On-Board Waveform Memory with Amplitude, Time, and Frequency Control
- Active Acceleration and Rapid Stop for High-Fidelity Haptic Feedback
- Continuous Actuator Diagnostics and Fault Handling
- No Software Requirements with Embedded Operation
- Differential Output Drive
- Current Driven System
- Configurable EMI Suppression
- Automatic Short Circuit Protection
- Ultra-Low Power Consumption with State Retention
- Ultra-Low Latency in STANDBY State
- Supply Monitoring, Reporting, and Automatic Output Limiting
- Open- and Closed-Loop Modes
- Open-Loop Sine/Custom Wave Drive Support
- Small Solution Footprint
- Additional Features
- 5.2 Functional Modes
- 5.3 Resonant Frequency Tracking
- 5.4 Active Acceleration and Rapid Stop
- 5.5 Wideband Frequency Control
- 5.6 Device Configuration and Playback
- 5.7 Advanced Operation
- 5.7.1 Frequency Tracking
- 5.7.2 Rapid Stop
- 5.7.3 Initial Impedance Update
- 5.7.4 Amplitude PID
- 5.7.5 Wideband Operation
- 5.7.6 Custom Waveform Operation
- 5.7.7 Embedded Operation
- 5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode
- 5.7.9 Loop Filter Configuration
- 5.7.10 UVLO Threshold
- 5.7.11 Edge Rate Control
- 5.7.12 Double Output Current Range
- 5.7.13 Supply Monitoring, Reporting, and Automatic Output Limiting
- 5.7.14 BEMF Fault Limit
- 5.7.15 Increasing Impedance Detection Accuracy
- 5.7.16 Frequency Pause during Rapid Stop
- 5.7.17 Frequency Pause during Rapid Stop
- 5.7.18 Coin ERM Operation
- 5.8 Waveform Memory
- 5.9 General Data Format
- 5.10 I2C Control Interface
- 5.1 Features Description
- 6 Register Overview
- 7 Package Information
- 8 Ordering Information
- 9 Application Information
- 10 Layout Guidelines
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Datasheet
Revision 3.0
30-Jul-2019
CFR0011-120-00
54 of 76
© 2019 Dialog Semiconductor
6 Register Overview
6.1 Register Map
All register bits classed as Reserved are Read-Only and can be ignored.
Table 19: Register Map
Addr
Register
7
6
5
4
3
2
1
0
Reset
0x00
CHIP_REV
CHIP_REV_MINOR<3:0>
CHIP_REV_MAJOR<3:0>
0xBA
0x03
IRQ_EVENT1
E_OC_F
AULT
E_ACTU
ATOR_F
AULT
E_WARN
ING
E_SEQ_F
AULT
E_OVERT
EMP_CRIT
E_SEQ_
DONE
E_UVLO
E_SEQ_
CONTIN
UE
0x00
0x04
IRQ_EVENT_
WARNING_D
IAG
E_LIM_D
RIVE
E_LIM_D
RIVE_AC
C
Reserved
E_MEM_T
YPE
E_OVERT
EMP_WAR
N
Reserved
Reserved
Reserve
d
0x00
0x05
IRQ_EVENT_
SEQ_DIAG
E_SEQ_I
D_FAUL
T
E_MEM_
FAULT
E_PWM_
FAULT
Reserved
Reserved
Reserved
Reserved
Reserve
d
0x00
0x06
IRQ_STATU
S1
STA_OC
STA_AC
TUATOR
STA_WA
RNING
STA_SEQ
_FAULT
STA_OVE
RTEMP_C
RIT
STA_SE
Q_DONE
STA_UVL
O_VBAT_
OK
STA_SE
Q_CON
TINUE
0x00
0x07
IRQ_MASK1
OC_M
ACTUAT
OR_M
WARNIN
G_M
SEQ_FAU
LT_M
OVERTEM
P_CRIT_M
SEQ_DO
NE_M
E_UVLO_
M
SEQ_C
ONTINU
E_M
0x00
0x08
CIF_I2C1
I2C_WR_
MODE
I2C_TO_
ENABLE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserve
d
0x40
0x0A
FRQ_LRA_P
ER_H
LRA_PER_H<7:0>
0x21
0x0B
FRQ_LRA_P
ER_L
Reserved
LRA_PER_L<6:0>
0x4F
0x0C
ACTUATOR1
ACTUATOR_NOMMAX<7:0>
0x5A
0x0D
ACTUATOR2
ACTUATOR_ABSMAX<7:0>
0x78
0x0E
ACTUATOR3
Reserved
Reserved
Reserved
IMAX<4:0>
0x17
0x0F
CALIB_V2I_H
V2I_FACTOR_H<7:0>
0x01
0x10
CALIB_V2I_L
V2I_FACTOR_L<7:0>
0x0D
0x11
CALIB_IMP_
H
IMPEDANCE_H<7:0>
0x00
0x12
CALIB_IMP_
L
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IMPEDANCE_L<1:0>
0x00
0x13
TOP_CFG1
EMBEDD
ED_MOD
E
Reserved
ACTUAT
OR_TYP
E
BEMF_SE
NSE_EN
FREQ_TR
ACK_EN
ACCELE
RATION_
EN
RAPID_S
TOP_EN
AMP_PI
D_EN
0x1E
0x14
TOP_CFG2
Reserved
Reserved
Reserved
MEM_DAT
A_SIGNED
FULL_BRAKE_THR<3:0>
0x01
0x15
TOP_CFG3
Reserved
Reserved
Reserved
Reserved
VDD_MARGIN<3:0>
0x03
0x16
TOP_CFG4
V2I_FAC
TOR_FR
EEZE
CALIB_I
MPEDAN
CE_DIS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserve
d
0x40
0x17
TOP_INT_CF
G1
FRQ_LOCKED_LIM<5:0>
BEMF_FAULT_LIM<1:
0>
0x81
0x1C
TOP_INT_CF
G6_H
FRQ_PID_Kp_H<7:0>
0x0E
0x1D
TOP_INT_CF
G6_L
FRQ_PID_Kp_L<7:0>
0x20
0x1E
TOP_INT_CF
G7_H
FRQ_PID_Ki_H<7:0>
0x03