Datasheet

DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Datasheet
Revision 3.0
30-Jul-2019
CFR0011-120-00
52 of 76
© 2019 Dialog Semiconductor
The I
2
C bus is monitored by DA7280 for a valid slave address whenever the interface is enabled. It
responds with an Acknowledge immediately when it receives its own slave address. The
Acknowledge is done by pulling the SDA line LOW during the following clock cycle (white blocks
marked with A in Figure 34 to Figure 38).
The protocol for a register write from master to slave consists of a START condition, a slave address
with read/write bit and the 8-bit register address followed by 8 bits of data terminated by a STOP
condition (DA7280 responds to all bytes with Acknowledge), see Figure 34.
SLAVE addr
W
REG addr
A
DATA
A
P
S = START condition A = Acknowledge (low)
P = STOP condition W = Write (low)
Master to Slave
Slave to Master
7-bits
1-bit
8-bits
8-bits
A
S
Figure 34: I
2
C Byte Write (SDA line)
When the host reads data from a register it first has to write access DA7280 with the target register
address and then read access DA7280 with a repeated START, or alternatively a second START
condition. After receiving the data the host sends a Not Acknowledge (NAK) and terminates the
transmission with a STOP condition:
S
SLAVEaddr
W
A
REG addr
A
SLAVEaddr
A
S = START condition A = Acknowledge (low)
Sr = Repeated START condition A
*
= Not Acknowledge (NAK)
P = STOP condition W = Write (low) R = Read (high)
Master to Slave
7-bits
1-bit
8-bits
7-bits
DATA
A
*
Sr
R
1-bit
8-bits
SLAVEaddr
A
7-bits
DATA
P
S
R
1-bit
8-bits
P
A
*
Slave to Master
S
SLAVEaddr
W
A
REG addr
P
7-bits
1-bit
8-bits
A
Figure 35: Examples of the I
2
C Byte Read (SDA line)
Consecutive (Page) Read-Out mode, I2C_WR_MODE (register CIF_I2C1) = 0, is initiated from the
master by sending an Acknowledge instead of Not Acknowledge (NAK) after receipt of the data word.
The I
2
C control block then increments the address pointer to the next I
2
C address and sends the data
to the master. This enables an unlimited read of data bytes until the master sends an NAK directly
after the receipt of data, followed by a subsequent STOP condition. If a non-existent I
2
C address is
read out, the DA7280 will return code zero.
S
SLAVEaddr
W
A
REG addr
A
SLAVEaddr
A
S = START condition A = Acknowledge (low)
Sr = Repeat START condition A
*
= Not Acknowledge (NAK)
P = STOP condition W = Write (low) R = Read (high)
Master to Slave
Slave to Master
7-bits
1 bit
8-bits
7-bits
DATA
A
Sr
R
1-bit
8-bits
S
SLAVEaddr
W
A
REG addr
A
SLAVEaddr
A
7-bits
1-bit
8-bits
7-bits
DATA
P
S
R
1-bit
8-bits
P
A
A
*
P
DATA
DATA
A
A
*
DATA
8-bits
8-bits
8-bits
Figure 36: Examples of I
2
C Page Read (SDA line)
In Page mode the slave address after Sr (Repeated START condition) must be the same as the
previous slave address.