Datasheet

DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Datasheet
Revision 3.0
30-Jul-2019
CFR0011-120-00
51 of 76
© 2019 Dialog Semiconductor
5.10 I
2
C Control Interface
DA7280 is software controlled from the host by registers accessed via an I
2
C compatible serial
control interface. Data is shifted into or out of the DA7280 under the control of the host processor,
which also provides the serial clock.
The DA7280 7-bit I
2
C slave address is 0x4A (1001010 binary), which is equivalent to 0x94 (8-bit) for
writing and 0x95 (8-bit) for reading.
The I
2
C clock is supplied by the SCL line and the bidirectional I
2
C data is carried by the SDA line.
The I
2
C interface is open-drain supporting multiple devices on a single line. The bus lines have to be
pulled HIGH by external pull-up resistors (1 kΩ to 20 kΩ range). The attached devices only drive the
bus lines LOW by connecting them to ground. This means that two devices cannot conflict if they
drive the bus simultaneously.
DA7280 supports Standard-mode, Fast-mode, and Fast-mode Plus, with the highest frequency of the
bus at 1 MHz in Fast-mode Plus. The exact frequency can be determined by the application and
does not have any relation to the DA7280 internal clock signals. DA7280 will follow the host clock
speed within the described limitations and does not initiate any clock arbitration or slow-down.
Communication on the I
2
C bus always takes place between two devices, one acting as the master
and the other as the slave. The DA7280 will only operate as a slave.
Host
Processor
DA7280
SDA
SCL
Peripheral
Device
SDA
SCL
SCL
SDA
VDDIO
VDDIO
Figure 32: Schematic of the I
2
C Control Interface Bus
All data is transmitted across the I
2
C bus in groups of eight bits. To send a bit the SDA line is driven
to the intended state while the SCL is LOW (a LOW on SCL indicates a zero bit). Once the SDA has
settled, the SCL line is brought HIGH and then LOW. This pulse on SCL clocks the SDA bit into the
receiver’s shift register.
A two-byte serial protocol is used containing one byte for address and one byte for data. Data and
address transfer is transmitted MSB first for both read and write operations. All transmission begins
with the START condition from the master while the bus is in the Idle mode (the bus is free). It is
initiated by a HIGH to LOW transition on the SDA line while the SCL is in the HIGH state (a STOP
condition is indicated by a LOW to HIGH transition on the SDA line while the SCL line is in the HIGH
state).
SCL
SDA
Figure 33: I
2
C START and STOP Conditions