Datasheet
Table Of Contents
- General Description
- Key Features
- Applications
- System Diagrams
- Contents
- Figures
- Tables
- Legal
- Product Family
- 1 Terms and Definitions
- 2 Block Diagram
- 3 Pinout
- 4 Characteristics
- 5 Functional Description
- 5.1 Features Description
- Driving LRA and ERM Actuators
- Automatic LRA Resonant Frequency Tracking
- Wideband LRA Support
- I2C and PWM Input Streaming
- Low Latency I2C/GPI Wake-Up from IDLE State
- Three GPI Sequence Triggers for up to Six Independent Haptic Responses
- On-Board Waveform Memory with Amplitude, Time, and Frequency Control
- Active Acceleration and Rapid Stop for High-Fidelity Haptic Feedback
- Continuous Actuator Diagnostics and Fault Handling
- No Software Requirements with Embedded Operation
- Differential Output Drive
- Current Driven System
- Configurable EMI Suppression
- Automatic Short Circuit Protection
- Ultra-Low Power Consumption with State Retention
- Ultra-Low Latency in STANDBY State
- Supply Monitoring, Reporting, and Automatic Output Limiting
- Open- and Closed-Loop Modes
- Open-Loop Sine/Custom Wave Drive Support
- Small Solution Footprint
- Additional Features
- 5.2 Functional Modes
- 5.3 Resonant Frequency Tracking
- 5.4 Active Acceleration and Rapid Stop
- 5.5 Wideband Frequency Control
- 5.6 Device Configuration and Playback
- 5.7 Advanced Operation
- 5.7.1 Frequency Tracking
- 5.7.2 Rapid Stop
- 5.7.3 Initial Impedance Update
- 5.7.4 Amplitude PID
- 5.7.5 Wideband Operation
- 5.7.6 Custom Waveform Operation
- 5.7.7 Embedded Operation
- 5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode
- 5.7.9 Loop Filter Configuration
- 5.7.10 UVLO Threshold
- 5.7.11 Edge Rate Control
- 5.7.12 Double Output Current Range
- 5.7.13 Supply Monitoring, Reporting, and Automatic Output Limiting
- 5.7.14 BEMF Fault Limit
- 5.7.15 Increasing Impedance Detection Accuracy
- 5.7.16 Frequency Pause during Rapid Stop
- 5.7.17 Frequency Pause during Rapid Stop
- 5.7.18 Coin ERM Operation
- 5.8 Waveform Memory
- 5.9 General Data Format
- 5.10 I2C Control Interface
- 5.1 Features Description
- 6 Register Overview
- 7 Package Information
- 8 Ordering Information
- 9 Application Information
- 10 Layout Guidelines
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Datasheet
Revision 3.0
30-Jul-2019
CFR0011-120-00
49 of 76
© 2019 Dialog Semiconductor
100 %
0
-100 %
0xF
0xE
0xD
.
.
.
0x2
0x1
0x0
N/A
N/A
N/A
.
.
.
N/A
N/A
0x7F
0x7E
0x7D
.
.
.
0x02
0x01
0x00
0xFF
0xFE
0xFD
.
.
.
0x81
0x80
PWM
[Mark / space]
DRO
MEM
FULL_BRAKE_THRS[3:0]
full brake
(only for PWM)
Drive positive direction
NO NEGATIVE DRIVE
mark – space ratio
100%
0%
Waveform/Data source
Driving Strength in ENV GEN
[%]
Data format for ERM and LRA
ACCELERATION_EN = 1
4 bits
uns.
8 bits
2's c.
Drive negative direction
Figure 31: Overview of Data Formats with Acceleration Enabled
5.9.1 DRO Mode
DRO data is supplied from I
2
C and is interpreted as 8-bit two’s complement signed number.
● For ACCELERATION_EN = 0:
○ The most negative value corresponds to -100 % driving strength.
○ The most positive value corresponds to +100 % driving strength.
○ A zero value corresponds to no drive.
○ The full range is between 127 (100 %) and -127 (-100 %), with -128 interpreted as -127 to
keep the ranges symmetrical.
● For ACCELERATION_EN = 1:
○ Negative values are omitted and substituted with zero.
○ The most positive value corresponds to +100 % driving strength.
○ Zero value corresponds to no drive.