Datasheet
Table Of Contents
- General Description
- Key Features
- Applications
- System Diagrams
- Contents
- Figures
- Tables
- Legal
- Product Family
- 1 Terms and Definitions
- 2 Block Diagram
- 3 Pinout
- 4 Characteristics
- 5 Functional Description
- 5.1 Features Description
- Driving LRA and ERM Actuators
- Automatic LRA Resonant Frequency Tracking
- Wideband LRA Support
- I2C and PWM Input Streaming
- Low Latency I2C/GPI Wake-Up from IDLE State
- Three GPI Sequence Triggers for up to Six Independent Haptic Responses
- On-Board Waveform Memory with Amplitude, Time, and Frequency Control
- Active Acceleration and Rapid Stop for High-Fidelity Haptic Feedback
- Continuous Actuator Diagnostics and Fault Handling
- No Software Requirements with Embedded Operation
- Differential Output Drive
- Current Driven System
- Configurable EMI Suppression
- Automatic Short Circuit Protection
- Ultra-Low Power Consumption with State Retention
- Ultra-Low Latency in STANDBY State
- Supply Monitoring, Reporting, and Automatic Output Limiting
- Open- and Closed-Loop Modes
- Open-Loop Sine/Custom Wave Drive Support
- Small Solution Footprint
- Additional Features
- 5.2 Functional Modes
- 5.3 Resonant Frequency Tracking
- 5.4 Active Acceleration and Rapid Stop
- 5.5 Wideband Frequency Control
- 5.6 Device Configuration and Playback
- 5.7 Advanced Operation
- 5.7.1 Frequency Tracking
- 5.7.2 Rapid Stop
- 5.7.3 Initial Impedance Update
- 5.7.4 Amplitude PID
- 5.7.5 Wideband Operation
- 5.7.6 Custom Waveform Operation
- 5.7.7 Embedded Operation
- 5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode
- 5.7.9 Loop Filter Configuration
- 5.7.10 UVLO Threshold
- 5.7.11 Edge Rate Control
- 5.7.12 Double Output Current Range
- 5.7.13 Supply Monitoring, Reporting, and Automatic Output Limiting
- 5.7.14 BEMF Fault Limit
- 5.7.15 Increasing Impedance Detection Accuracy
- 5.7.16 Frequency Pause during Rapid Stop
- 5.7.17 Frequency Pause during Rapid Stop
- 5.7.18 Coin ERM Operation
- 5.8 Waveform Memory
- 5.9 General Data Format
- 5.10 I2C Control Interface
- 5.1 Features Description
- 6 Register Overview
- 7 Package Information
- 8 Ordering Information
- 9 Application Information
- 10 Layout Guidelines
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Datasheet
Revision 3.0
30-Jul-2019
CFR0011-120-00
37 of 76
© 2019 Dialog Semiconductor
Configure the following bits to enable custom waveform operation:
● BEMF_SENSE_EN = 0
● WAVEGEN_MODE = 1
● V2I_FACTOR_FREEZE = 1
● DELAY_H = 0
● DELAY_SHIFT_L = 0
● DELAY_FREEZE = 1
● ACCELERATION_EN = 0
● RAPID_STOP_EN = 0
● AMP_PID_EN = 0
After the above setup is executed, amplitude data can be streamed in any mode, see Section 5.6.5,
and output frequency can be updated, see Section 5.7.6.
5.7.7 Embedded Operation
Should DA7280 be required to operate in a setup where no host is present or due to software
limitations unable to communicate with the device during its required operation, DA7280 can operate
in embedded operation by setting EMBEDDED_MODE = 1. In this case DA7280 is configured to
clear all system faults as it enters inactive mode when playback is finished or if a fault has been
detected, see Section 5.6.6.
For example, if a short circuit occurs, the system will react in its usual way: stop driving, disable the
current loop, and go to Inactive mode. Once in Inactive mode, the generated interrupt is
automatically cleared and DA7280 will attempt to drive again on the next playback request without
the host having to come in and clear faults.
5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode
For advanced sequence playback in DRO mode, the host may require DA7280 to update the output
drive amplitude every half period. Since the I
2
C clock is asynchronous to the DA7280 internal clock
and the exact timing of the half-period will change dynamically based on the frequency tracking loop,
this is not a trivial operation.
To overcome this limitation, the register POLARITY provides feedback. POLARITY toggles at the
start of every half-period (so at a rate of 400 Hz for a 200 Hz resonant frequency actuator). This
allows software synchronization of the updates to the OVERRIDE_VAL, see Figure 19.
Did POLARITY
toggle?
Update
OVERRIDE_VAL
Wait 25 µs
Yes
Read POLARITY
register
No
Figure 19: Half-Period Control in DRO Mode