Datasheet
Table Of Contents
- General Description
- Key Features
- Applications
- System Diagrams
- Contents
- Figures
- Tables
- Legal
- Product Family
- 1 Terms and Definitions
- 2 Block Diagram
- 3 Pinout
- 4 Characteristics
- 5 Functional Description
- 5.1 Features Description
- Driving LRA and ERM Actuators
- Automatic LRA Resonant Frequency Tracking
- Wideband LRA Support
- I2C and PWM Input Streaming
- Low Latency I2C/GPI Wake-Up from IDLE State
- Three GPI Sequence Triggers for up to Six Independent Haptic Responses
- On-Board Waveform Memory with Amplitude, Time, and Frequency Control
- Active Acceleration and Rapid Stop for High-Fidelity Haptic Feedback
- Continuous Actuator Diagnostics and Fault Handling
- No Software Requirements with Embedded Operation
- Differential Output Drive
- Current Driven System
- Configurable EMI Suppression
- Automatic Short Circuit Protection
- Ultra-Low Power Consumption with State Retention
- Ultra-Low Latency in STANDBY State
- Supply Monitoring, Reporting, and Automatic Output Limiting
- Open- and Closed-Loop Modes
- Open-Loop Sine/Custom Wave Drive Support
- Small Solution Footprint
- Additional Features
- 5.2 Functional Modes
- 5.3 Resonant Frequency Tracking
- 5.4 Active Acceleration and Rapid Stop
- 5.5 Wideband Frequency Control
- 5.6 Device Configuration and Playback
- 5.7 Advanced Operation
- 5.7.1 Frequency Tracking
- 5.7.2 Rapid Stop
- 5.7.3 Initial Impedance Update
- 5.7.4 Amplitude PID
- 5.7.5 Wideband Operation
- 5.7.6 Custom Waveform Operation
- 5.7.7 Embedded Operation
- 5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode
- 5.7.9 Loop Filter Configuration
- 5.7.10 UVLO Threshold
- 5.7.11 Edge Rate Control
- 5.7.12 Double Output Current Range
- 5.7.13 Supply Monitoring, Reporting, and Automatic Output Limiting
- 5.7.14 BEMF Fault Limit
- 5.7.15 Increasing Impedance Detection Accuracy
- 5.7.16 Frequency Pause during Rapid Stop
- 5.7.17 Frequency Pause during Rapid Stop
- 5.7.18 Coin ERM Operation
- 5.8 Waveform Memory
- 5.9 General Data Format
- 5.10 I2C Control Interface
- 5.1 Features Description
- 6 Register Overview
- 7 Package Information
- 8 Ordering Information
- 9 Application Information
- 10 Layout Guidelines
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Datasheet
Revision 3.0
30-Jul-2019
CFR0011-120-00
21 of 76
© 2019 Dialog Semiconductor
When driving a wideband LRA in DRO mode, resonant frequency tracking can be turned off. This
enables wideband operation and two-dimensional effects using DMAs, see Sections 5.7.5 and 5.7.6.
During playback, if a value written to OVERRIDE_VAL results in the output driving strength being
maintained at 0 %, DA7280 will disable its output stage to save power. Drive is re-enabled
automatically, with one LRA half-period delay, when a non-zero OVERRIDE_VAL value I
2
C input is
received.
5.2.5 Pulse Width Modulation Mode
PWM mode is used to stream haptic sequences to DA7280 via the GPI_0/PWM input pin where the
output drive level is determined by the duty cycle of the PWM signal. For optimal start-up timing, the
PWM input signal needs to be provided before setting OPERATION_MODE = 2. The PWM duty
cycle can be interpreted in two ways as follows:
If ACCELERATION_EN = 1, the output drive level is equal to the input signal duty cycle multiplied by
the voltage stored in ACTUATOR_NOMMAX. In this case the duty cycle is interpreted as a
proportion between 0 % and 100 %, see Figure 30. The automatic Active Acceleration and Rapid
Stop (if enabled) features will take the output up to the voltage in ACTUATOR_ABSMAX and/or
reverse the drive level to be negative during level transitions, but in steady state the final value will
always scale to the voltage in ACTUATOR_NOMMAX.
If ACCELERATION_EN = 0, the output drive level is equal to the input signal duty cycle multiplied by
the voltage stored in ACTUATOR_ABSMAX. In this case the duty cycle is interpreted as a proportion
between -100 % and 100 % where 50 % duty cycle is 0 %, see Figure 31. When DA7280 is set up to
drive an ERM, the negative value represents a change in drive voltage polarity, while for an LRA it
represents a phase shift of 180° in the drive signal. Negative drive can be used to speed up output
acceleration level changes without the use of the Active Acceleration and Rapid Stop. Note that in
the ACCELERATION_EN = 0 case Rapid Stop can still be enabled if an automatic stop to zero
actuator acceleration is required.
Note: The output PWM frequency is always independent of the PWM input frequency regardless of
whether frequency tracking is enabled or disabled. To maximize accuracy and minimize power
consumption and noise, it is best to keep the input PWM frequency as low as possible.
The PWM demodulator is rising edge sensitive. The minimum duty cycle that can be used to create
the drive level can be configured in FULL_BRAKE_THR; any duty cycle below that value will produce
a 0 % drive level.
During playback streaming in PWM mode, if a 0 % drive level is maintained by applying a 0 % (or
50 % if Active Acceleration is disabled) duty cycle PWM input, the DA7280 output stage is disabled
to save power. Drive is re-enabled automatically, with one LRA half-period delay, when the duty
cycle forces the drive level to be greater than 0 %.
ACCELERATION_EN = 0,
60% Duty Cycle
ACCELERATION_EN = 0,
90% Duty Cycle
ACCELERATION_EN = 0,
50% Duty Cycle
ACCELERATION_EN = 0,
40% Duty Cycle
ACCELERATION_EN = 0,
10% Duty Cycle
PWM
Signal
DA7280
Output
Figure 9: Example PWM Inputs with ACCELERATION_EN = 0
Note the 180° phase difference between driving > 50 % and < 50 %.