Datasheet
Table Of Contents
- General Description
- Key Features
- Applications
- System Diagrams
- Contents
- Figures
- Tables
- Legal
- Product Family
- 1 Terms and Definitions
- 2 Block Diagram
- 3 Pinout
- 4 Characteristics
- 5 Functional Description
- 5.1 Features Description
- Driving LRA and ERM Actuators
- Automatic LRA Resonant Frequency Tracking
- Wideband LRA Support
- I2C and PWM Input Streaming
- Low Latency I2C/GPI Wake-Up from IDLE State
- Three GPI Sequence Triggers for up to Six Independent Haptic Responses
- On-Board Waveform Memory with Amplitude, Time, and Frequency Control
- Active Acceleration and Rapid Stop for High-Fidelity Haptic Feedback
- Continuous Actuator Diagnostics and Fault Handling
- No Software Requirements with Embedded Operation
- Differential Output Drive
- Current Driven System
- Configurable EMI Suppression
- Automatic Short Circuit Protection
- Ultra-Low Power Consumption with State Retention
- Ultra-Low Latency in STANDBY State
- Supply Monitoring, Reporting, and Automatic Output Limiting
- Open- and Closed-Loop Modes
- Open-Loop Sine/Custom Wave Drive Support
- Small Solution Footprint
- Additional Features
- 5.2 Functional Modes
- 5.3 Resonant Frequency Tracking
- 5.4 Active Acceleration and Rapid Stop
- 5.5 Wideband Frequency Control
- 5.6 Device Configuration and Playback
- 5.7 Advanced Operation
- 5.7.1 Frequency Tracking
- 5.7.2 Rapid Stop
- 5.7.3 Initial Impedance Update
- 5.7.4 Amplitude PID
- 5.7.5 Wideband Operation
- 5.7.6 Custom Waveform Operation
- 5.7.7 Embedded Operation
- 5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode
- 5.7.9 Loop Filter Configuration
- 5.7.10 UVLO Threshold
- 5.7.11 Edge Rate Control
- 5.7.12 Double Output Current Range
- 5.7.13 Supply Monitoring, Reporting, and Automatic Output Limiting
- 5.7.14 BEMF Fault Limit
- 5.7.15 Increasing Impedance Detection Accuracy
- 5.7.16 Frequency Pause during Rapid Stop
- 5.7.17 Frequency Pause during Rapid Stop
- 5.7.18 Coin ERM Operation
- 5.8 Waveform Memory
- 5.9 General Data Format
- 5.10 I2C Control Interface
- 5.1 Features Description
- 6 Register Overview
- 7 Package Information
- 8 Ordering Information
- 9 Application Information
- 10 Layout Guidelines
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Datasheet
Revision 3.0
30-Jul-2019
CFR0011-120-00
20 of 76
© 2019 Dialog Semiconductor
5.2.2 Operating Modes
DA7280 offers multiple operating modes for use in different applications and to minimize power
consumption, see Table 12.
Table 12: Operating Modes
Operating Mode
Description
OPERATION_MODE
Inactive
System waits in IDLE or STANDBY state based on
STANDBY_EN setting
0
Direct register override (DRO)
Playback streaming via I
2
C; input written to
OVERRIDE_VAL
1
Pulse width modulated (PWM)
Playback streaming from PWM data input source on
pin GPI_0/PWM
2
Register triggered waveform
memory (RTWM)
Playback from Waveform Memory triggered only by
I
2
C write to SEQ_START
3
Edge triggered waveform
memory (ETWM)
Playback from Waveform Memory triggered by
rising/falling edge on any of three GPIs or via I
2
C write
to SEQ_START
4
5.2.3 Inactive Mode
DA7280 can be configured to automatically return to IDLE state (for lower I
Q
) or STANDBY state (for
minimized latency) after completion of playback, see Section 5.2.1. In both states the register
contents are retained. DA7280 remains in Inactive mode until it receives a playback request via
either the GPI pins or I
2
C (providing any faults in the fault registers have been cleared, see
Section 5.6.6).
In the event of a fault the system will automatically return to the IDLE state, see Section 5.6.6.
5.2.4 Direct Register Override Mode
In DRO mode haptic sequences are streamed to DA7280 via I
2
C input. The drive level of the output
is set via OVERRIDE_VAL. For optimal start-up timing, update OVERRIDE_VAL before setting
OPERATION_MODE = 1. OVERRIDE_VAL is treated as a two's complement proportional value
where:
If ACCELERATION_EN = 1, the output drive level is equal to the value in OVERRIDE_VAL multiplied
by the voltage stored in ACTUATOR_NOMMAX. OVERRIDE_VAL is interpreted as a proportion
between 0 % (0x00) and 100 % (0x7F). The range from 0xFF to 0x80 is not used, see Figure 30. If
enabled, the automatic Active Acceleration and Rapid Stop features will take the output up to the
voltage in ACTUATOR_ABSMAX and/or reverse the drive level to be negative during level
transitions, but in steady state the value will always scale to the voltage in ACTUATOR_NOMMAX.
If ACCELERATION_EN = 0, the output drive level is equal to the value in OVERRIDE_VAL multiplied
by the voltage stored in ACTUATOR_ABSMAX. In this case OVERRIDE_VAL is interpreted as a
proportion between -100% (0x80) and 100% (0x7F), see Figure 31. When DA7280 is set up to drive
an ERM, the negative value represents a change in drive voltage polarity, while for an LRA it
represents a phase shift of 180° in the drive signal. Negative drive can be used to speed up output
acceleration level changes without the use of the Active Acceleration and Rapid Stop. Note that in
the ACCELERATION_EN = 0 case Rapid Stop can still be enabled if an automatic stop to zero
actuator acceleration is required.
Note: The output amplitude updates at twice the LRA frequency (when the differential voltage across
the LRA crosses zero), therefore input changes more frequent than this are not required as sampling
occurs only around a zero cross. Since the I
2
C is asynchronous to the output drive, updates to
OVERRIDE_VAL will have a one LRA half-period of uncertainty before propagating to the output.
Synchronization of OVERRIDE_VAL updates to the half period is possible via software by looking at
the POLARITY register and updating the output drive level, see Section 5.7.8.